156 research outputs found

    Systematic redundant residue number system codes: analytical upper bound and iterative decoding performance over AWGN and Rayleigh channels

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    The novel family of redundant residue number system (RRNS) codes is studied. RRNS codes constitute maximum–minimum distance block codes, exhibiting identical distance properties to Reed–Solomon codes. Binary to RRNS symbol-mapping methods are proposed, in order to implement both systematic and nonsystematic RRNS codes. Furthermore, the upper-bound performance of systematic RRNS codes is investigated, when maximum-likelihood (ML) soft decoding is invoked. The classic Chase algorithm achieving near-ML soft decoding is introduced for the first time for RRNS codes, in order to decrease the complexity of the ML soft decoding. Furthermore, the modified Chase algorithm is employed to accept soft inputs, as well as to provide soft outputs, assisting in the turbo decoding of RRNS codes by using the soft-input/soft-output Chase algorithm. Index Terms—Redundant residue number system (RRNS), residue number system (RNS), turbo detection

    Near-capacity dirty-paper code design : a source-channel coding approach

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    This paper examines near-capacity dirty-paper code designs based on source-channel coding. We first point out that the performance loss in signal-to-noise ratio (SNR) in our code designs can be broken into the sum of the packing loss from channel coding and a modulo loss, which is a function of the granular loss from source coding and the target dirty-paper coding rate (or SNR). We then examine practical designs by combining trellis-coded quantization (TCQ) with both systematic and nonsystematic irregular repeat-accumulate (IRA) codes. Like previous approaches, we exploit the extrinsic information transfer (EXIT) chart technique for capacity-approaching IRA code design; but unlike previous approaches, we emphasize the role of strong source coding to achieve as much granular gain as possible using TCQ. Instead of systematic doping, we employ two relatively shifted TCQ codebooks, where the shift is optimized (via tuning the EXIT charts) to facilitate the IRA code design. Our designs synergistically combine TCQ with IRA codes so that they work together as well as they do individually. By bringing together TCQ (the best quantizer from the source coding community) and EXIT chart-based IRA code designs (the best from the channel coding community), we are able to approach the theoretical limit of dirty-paper coding. For example, at 0.25 bit per symbol (b/s), our best code design (with 2048-state TCQ) performs only 0.630 dB away from the Shannon capacity

    The Design of Efficiently-Encodable Rate-Compatible LDPC Codes

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    We present a new class of irregular low-density parity-check (LDPC) codes for moderate block lengths (up to a few thousand bits) that are well-suited for rate-compatible puncturing. The proposed codes show good performance under puncturing over a wide range of rates and are suitable for usage in incremental redundancy hybrid-automatic repeat request (ARQ) systems. In addition, these codes are linear-time encodable with simple shift-register circuits. For a block length of 1200 bits the codes outperform optimized irregular LDPC codes and extended irregular repeat-accumulate (eIRA) codes for all puncturing rates 0.6~0.9 (base code performance is almost the same) and are particularly good at high puncturing rates where good puncturing performance has been previously difficult to achieve.Comment: Accepted subject to minor revision to IEEE Trans. on Com

    The Design of Efficiently-Encodable Rate-Compatible LDPC Codes

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    We present a new class of irregular low-density parity-check (LDPC) codes for moderate block lengths (up to a few thousand bits) that are well-suited for rate-compatible puncturing. The proposed codes show good performance under puncturing over a wide range of rates and are suitable for usage in incremental redundancy hybrid-automatic repeat request (ARQ) systems. In addition, these codes are linear-time encodable with simple shift-register circuits. For a block length of 1200 bits the codes outperform optimized irregular LDPC codes and extended irregular repeat-accumulate (eIRA) codes for all puncturing rates 0.6~0.9 (base code performance is almost the same) and are particularly good at high puncturing rates where good puncturing performance has been previously difficult to achieve
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