Electrical Tests for Capacitive Open Defects in Assembled PCBs

Nowadays, Ball Grid Array (BGA) becomes a major packaging type due to its high bulk for input/output (I/O) pins. However, there are defects such as voids and cracks occurring between a BGA IC and a PCB which may result in an electrical failure in the circuit. This paper presents electrical tests for capacitive open defects occurring at an interconnection between an IC and a PCB. Feasibility of the electrical test with the test circuit is evaluated by SPICE simulation and experiments. Capacitive open defects occurring at interconnects are detected by the test method. Both simulation and experimental results showed that capacitive open defects generating no logical errors can be detected by the test method at a test speed of 1kHz and 1MHz

Detection of Interconnect Failure Precursors using RF Impedance Analysis

Many failures in electronics result from the loss of electrical continuity of common board-level interconnects such as solder joints. Measurement methods based on DC resistance such as event detectors and data-loggers have long been used by the electronics industry to monitor the reliability of interconnects during reliability testing. DC resistance is well-suited for characterizing electrical continuity, such as identifying an open circuit, but it is not useful for detecting a partially degraded interconnect. Degradation of interconnects, such as cracking of solder joints due to fatigue or shock loading, usually initiates at an exterior surface and propagates towards the interior. A partially degraded interconnect can cause the RF impedance to increase due to the skin effect, a phenomenon wherein signal propagation at frequencies above several hundred MHz is concentrated at the surface of a conductor. Therefore, RF impedance exhibits greater sensitivity compared to DC resistance in detecting early stages of interconnect degradation and provides a means to prevent and predict an important cause of electronics failures. This research identifies the applicability of RF impedance as a means of a failure precursor that allows for prognostics on interconnect degradation based on electrical measurement. It also compares the ability of RF impedance with that of DC resistance to detect early stages of interconnect degradation, and to predict the remaining life of an interconnect. To this end, RF impedance and DC resistance of a test circuit were simultaneously monitored during interconnect stress testing. The test vehicle included an impedance-controlled circuit board on which a surface mount component was soldered using two solder joints at the end terminations. During stress testing, the RF impedance exhibited a gradual non-linear increase in response to the early stages of solder joint cracking while the DC resistance remained constant. The gradual increase in RF impedance was trended using prognostic algorithms in order to predict the time to failure of solder joints. This prognostic approach successfully predicted solder joint remaining life with a prediction error of less than 3%. Furthermore, it was demonstrated both theoretically and experimentally that the RF impedance analysis was able to distinguish between two competing interconnect failure mechanisms: solder joint cracking and pad cratering. These results indicate that RF impedance provides reliable interconnect failure precursors that can be used to predict interconnect failures. Since the performance of high speed devices is adversely affected by early stages of interconnect degradation, RF impedance analysis has the potential to provide improved reliability assessment for these devices, as well as accurate failure prediction for current and future electronics

Developing Trustworthy Hardware with Security-Driven Design and Verification

Over the past several decades, computing hardware has evolved to become smaller, yet more performant and energy-efficient. Unfortunately these advancements have come at a cost of increased complexity, both physically and functionally. Physically, the nanometer-scale transistors used to construct Integrated Circuits (ICs), have become astronomically expensive to fabricate. Functionally, ICs have become increasingly dense and feature rich to optimize application-specific tasks. To cope with these trends, IC designers outsource both fabrication and portions of Register-Transfer Level (RTL) design. Outsourcing, combined with the increased complexity of modern ICs, presents a security risk: we must trust our ICs have been designed and fabricated to specification, i.e., they do not contain any hardware Trojans. Working in a bottom-up fashion, I initially study the threat of outsourcing fabrication. While prior work demonstrates fabrication-time attacks (modifications) on IC layouts, it is unclear what makes a layout vulnerable to attack. To answer this, in my IC Attack Surface (ICAS) work, I develop a framework that quantifies the security of IC layouts. Using ICAS, I show that modern ICs leave a plethora of both placement and routing resources available for attackers to exploit. Next, to plug these gaps, I construct the first routing-centric defense (T-TER) against fabrication-time Trojans. T-TER wraps security-critical interconnects in IC layouts with tamper-evident guard wires to prevent foundry-side attackers from modifying a design. After hardening layouts against fabrication-time attacks, outsourced designs become the most critical threat. To address this, I develop a dynamic verification technique (Bomberman) to vet untrusted third-party RTL hardware for Ticking Timebomb Trojans (TTTs). By targeting a specific type of Trojan behavior, Bomberman does not suffer from false negatives (missed TTTs), and therefore systematically reduces the overall design-time attack surface. Lastly, to generalize the Bomberman approach to automatically discover other behaviorally-defined classes of malicious logic, I adapt coverage-guided software fuzzers to the RTL verification domain. Leveraging software fuzzers for RTL verification enables IC design engineers to optimize test coverage of third-party designs without intimate implementation knowledge. Overall, this dissertation aims to make security a first-class design objective, alongside power, performance, and area, throughout the hardware development process.PHDComputer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/169761/1/trippel_1.pd