Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Ultra Low Energy Analog Image Processing Using Spin Neurons

In this work we present an ultra low energy, 'on-sensor' image processing architecture, based on cellular array of spin based neurons. The 'neuron' constitutes of a lateral spin valve (LSV) with multiple input magnets, connected to an output magnet, using metal channels. The low resistance, magneto-metallic neurons operate at a small terminal voltage of ~20mV, while performing analog computation upon photo sensor inputs. The static current-flow across the device terminals is limited to small periods, corresponding to magnet switching time, and, is determined by a low duty-cycle system-clock. Thus, the energy-cost of analog-mode processing, inevitable in most image sensing applications, is reduced and made comparable to that of dynamic and leakage power consumption in peripheral CMOS units. Performance of the proposed architecture for some common image sensing and processing applications like, feature extraction, halftone compression and digitization, have been obtained through physics based device simulation framework, coupled with SPICE. Results indicate that the proposed design scheme can achieve more than two orders of magnitude reduction in computation energy, as compared to the state of art CMOS designs, that are based on conventional mixed-signal image acquisition and processing schemes. To the best of authors' knowledge, this is the first work where application of nano magnets (in LSV's) in analog signal processing has been proposed

Improving Accuracy and Energy Efficiency of Pipeline Analog to Digital Converters

Analog-to-Digital converters (ADC) are key building blocks of analog and mixed-signal processing that link the natural world of analog signals and the world of digital processing. This work describes the analysis, design, development and test of novel high-resolution (≥12-bit), moderate speed (10-100MS/s), energy-efficient ADCs. Such ADCs are typically used for communication, imaging and video applications. CMOS process scaling is typically aimed at enabling fast, low-power digital circuits. Scaling leads to lower supply voltages, and to short channel devices with low gain and poor matching between small devices. On the other hand, to process and amplify analog signals analog circuits rely on wide signal swing, large transistor gain and good component matching. Hence, analog circuit performance has lagged far behind digital performance. Analog circuits such as ADCs are therefore nowadays performance bottlenecks in many electronic systems. The pipeline ADC is a popular architecture for implementing ADCs with a wide range of speed and resolution. This work aims to improve the accuracy and energy efficiency of the pipeline architecture by combining it with more accurate or more energy efficient architectures such as Sigma-Delta and Successive-Approximation (SAR). Such novel, hybrid architectures are investigated in this work. In the first design, a new architecture is developed which combines a low-OSR resetting Sigma-Delta modulator architecture with the pipeline architecture. This architecture enhances the accuracy and energy efficiency of the pipeline architecture. A prototype 14-bit 23MS/s ADC, based on this new architecture, is designed and tested. This ADC achieves calibration-free 14-bit linearity, 11.7-bit ENOB and 87dB SFDR while dissipating only 48mW of power. In the second design, new hybrid architecture based on SAR and pipeline architecture is developed. This architecture significantly improves the energy efficiency of the pipeline architecture. A prototype 12-bit 50MS/s ADC is designed based on this new architecture. “Half-gain” and “half-reference” pipeline stages are also introduced in this prototype for the first time to further reduce power dissipation. This ADC dissipates only 3.5mW power.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/76025/1/leechun_1.pd

Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications

As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced. This warrants more interest in analog-to-digital converter (ADC)-based serial link receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) relative to binary or mixed-signal receivers. Utilizing this back-end DSP allows for complex digital equalization and more bandwidth-efficient modulation schemes, while also displaying reduced process/voltage/temperature (PVT) sensitivity. Furthermore, these architectures offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes. However, the power consumption of the ADC front-end and subsequent digital signal processing is a major issue. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-effcient receiver. This dissertation presents efficient implementations for multi-GS/s time-interleaved ADCs with partial embedded equalization. First prototype details a 6b 1.6GS/s ADC with a novel embedded redundant-cycle 1-tap DFE structure in 90nm CMOS. The other two prototypes explain more complex 6b 10GS/s ADCs with efficiently embedded feed-forward equalization (FFE) and decision feedback equalization (DFE) in 65nm CMOS. Leveraging a time-interleaved successive approximation ADC architecture, new structures for embedded DFE and FFE are proposed with low power/area overhead. Measurement results over FR4 channels verify the effectiveness of proposed embedded equalization schemes. The comparison of fabricated prototypes against state-of-the-art general-purpose ADCs at similar speed/resolution range shows comparable performances, while the proposed architectures include embedded equalization as well

Voltage-to-Time Converter for High-Speed Time-Based Analog-to-Digital Converters

In modern complementary metal oxide semiconductor (CMOS) technologies, the supply voltage scales faster than the threshold voltage (Vth) of the transistors in successive smaller nodes. Moreover, the intrinsic gain of the transistors diminishes as well. Consequently, these issues increase the difficulty of designing higher speed and larger resolution analog-to-digital converters (ADCs) employing voltage-domain ADC architectures. Nevertheless, smaller transistor dimensions in state-of-the-art CMOS technologies leads to reduced capacitance, resulting in lower gate delays. Therefore, it becomes beneficial to first convert an input voltage to a 'time signal' using a voltage-to-time converter (VTC), instead of directly converting it into a digital output. This 'time-signal' could then be converted to a digital output through a time-to-digital converter (TDC) for complete analog-to-digital conversion. However, the overall performance of such an ADC will still be limited to the performance level of the voltage-to-time conversion process. Hence, this thesis presents the design of a linear VTC for a high-speed time-based ADC in 28 nm CMOS process. The proposed VTC consists of a sample-and-hold (S/H) circuit, a ramp generator and a comparator to perform the conversion of the input signal from the voltage to the time domain. Larger linearity is attained by integrating a constant current (with high output impedance) over a capacitor, generating a linear ramp. The VTC operates at 256 MSPS consuming 1.3 mW from 1 V supply with a full-scale 1 V pk-pk differential input signal, while achieving a time-domain output signal with a spurious-free-dynamic-range (SFDR) of 77 dB and a signal-to-noise-and-distortion ratio (SNDR) of 56 dB at close to Nyquist frequency (f = 126.5 MHz). The proposed VTC attains an output range of 2.7 ns, which is the highest linear output range for a VTC at this speed, published to date

Digital Background Self-Calibration Technique for Compensating Transition Offsets in Reference-less Flash ADCs

This Dissertation focusses on proving that background calibration using adaptive algorithms are low-cost, stable and effective methods for obtaining high accuracy in flash A/D converters. An integrated reference-less 3-bit flash ADC circuit has been successfully designed and taped out in UMC 180 nm CMOS technology in order to prove the efficiency of our proposed background calibration. References for ADC transitions have been virtually implemented built-in in the comparators dynamic-latch topology by a controlled mismatch added to each comparator input front-end. An external very simple DAC block (calibration bank) allows control the quantity of mismatch added in each comparator front-end and, therefore, compensate the offset of its effective transition with respect to the nominal value. In order to assist to the estimation of the offset of the prototype comparators, an auxiliary A/D converter with higher resolution and lower conversion speed than the flash ADC is used: a 6-bit capacitive-DAC SAR type. Special care in synchronization of analogue sampling instant in both ADCs has been taken into account. In this thesis, a criterion to identify the optimum parameters of the flash ADC design with adaptive background calibration has been set. With this criterion, the best choice for dynamic latch architecture, calibration bank resolution and flash ADC resolution are selected. The performance of the calibration algorithm have been tested, providing great programmability to the digital processor that implements the algorithm, allowing to choose the algorithm limits, accuracy and quantization errors in the arithmetic. Further, systematic controlled offset can be forced in the comparators of the flash ADC in order to have a more exhaustive test of calibration

Aika-digitaalimuunnin laajakaistaisiin aikapohjaisiin analogia-digitaalimuuntimiin

Modern deeply scaled semiconductor processes make the design of voltage-domain circuits increasingly challenging. On the contrary, the area and power consumption of digital circuits are improving with every new process node. Consequently, digital solutions are designed in place of their purely analog counterparts in applications such as analog-to-digital (A/D) conversion. Time-based analog-to-digital converters (ADC) employ digital-intensive architectures by processing analog quantities in time-domain. The quantization step of the time-based A/D-conversion is carried out by a time-to-digital converter (TDC). A free-running ring oscillator -based TDC design is presented for use in wideband time-based ADCs. The proposed architecture aims to maximize time resolution and full-scale range, and to achieve error resilient conversion performance with minimized power and area consumptions. The time resolution is maximized by employing a high-frequency multipath ring oscillator, and the full-scale range is extended using a high-speed gray counter. The error resilience is achieved by custom sense-amplifier -based sampling flip-flops, gray coded counter and a digital error correction algorithm for counter sampling error correction. The implemented design achieves up to 9-bit effective resolution at 250 MS/s with 4.3 milliwatt power consumption.Modernien puolijohdeteknologioiden skaalautumisen seurauksena jännitetason piirien suunnittelu tulee entistä haasteellisemmaksi. Toisaalta digitaalisten piirirakenteiden pinta-ala sekä tehonkulutus pienenevät prosessikehityksen myötä. Tästä syystä digitaalisia ratkaisuja suunnitellaan vastaavien puhtaasti analogisien rakenteiden tilalle. Analogia-digitaalimuunnos (A/D-muunnos) voidaan toteuttaa jännitetason sijaan aikatasossa käyttämällä aikapohjaisia A/D-muuntimia, jotka ovat rakenteeltaan pääosin digitaalisia. Kvantisointivaihe aikapohjaisessa A/D-muuntimessa toteutetaan aika-digitaalimuuntimella. Työ esittelee vapaasti oskilloivaan silmukkaoskillaattoriin perustuvan aika-digitaalimuuntimen, joka on suunniteltu käytettäväksi laajakaistaisessa aikapohjaisessa A/D-muuntimessa. Esitelty rakenne pyrkii maksimoimaan muuntimen aikaresoluution sekä muunnosalueen, sekä saavuttamaan virhesietoisen muunnostoiminnan minimoidulla tehon sekä pinta-alan kulutuksella. Aikaresoluutio on maksimoitu hyödyntämällä suuritaajuista monipolkuista silmukkaoskillaattoria, ja muunnosalue on maksimoitu nopealla Gray-koodi -laskuripiirillä. Muunnosprosessin virhesietoisuus on saavutettu toteuttamalla näytteistys herkillä kiikkuelementeillä, hyödyntämällä Gray-koodattua laskuria, sekä jälkiprosessoimalla laskurin näytteistetyt arvot virheenkorjausalgoritmilla. Esitelty muunnintoteutus saavuttaa 9 bitin efektiivisen resoluution 250 MS/s näytetaajuudella ja 4.3 milliwatin tehonkulutuksella

Low Power Analog to Digital Converters in Advanced CMOS Technology Nodes

The dissertation presents system and circuit solutions to improve the power efficiency and address high-speed design issues of ADCs in advanced CMOS technologies. For image sensor applications, a high-performance digitizer prototype based on column-parallel single-slope ADC (SS-ADC) topology for readout of a back-illuminated 3D-stacked CMOS image sensor is presented. To address the high power consumption issue in high-speed digital counters, a passing window (PW) based hybrid counter topology is proposed. To address the high column FPN under bright illumination conditions, a double auto-zeroing (AZ) scheme is proposed. The proposed techniques are experimentally verified in a prototype chip designed and fabricated in the TSMC 40 nm low-power CMOS process. The PW technique saves 52.8% of power consumption in the hybrid digital counters. Dark/bright column fixed pattern noise (FPN) of 0.0024%/0.028% is achieved employing the proposed double AZ technique for digital correlated double sampling (CDS). A single-column digitizer consumes total power of 66.8μW and occupies an area of 5.4 µm x 610 µm. For mobile/wireless receiver applications, this dissertation presents a low-power wide-bandwidth multistage noise-shaping (MASH) continuous-time delta-sigma modulator (CT-ΔΣM) employing finite impulse response (FIR) digital-to-analog converters (DACs) and encoder-embedded loop-unrolling (EELU) quantizers. The proposed MASH 1-1-1 topology is a cascade of three single-loop first-order CT-ΔΣM stages, each of which consists of an active-RC integrator, a current-steering DAC, and an EELU quantizer. An FIR filter in the main 1.5-bit DAC improves the modulator’s jitter sensitivity performance. FIR’s effect on the noise transfer function (NTF) of the modulator is compensated in the digital domain thanks to the MASH topology. Instead of employing a conventional analog direct feedback path, a 1.5-bit EELU quantizer based on multiplexing comparator outputs is proposed; this approach is suitable for highspeed operation together with power and area benefits. Fabricated in a 40-nm low-power CMOS technology, the modulator’s prototype achieves a 67.3 dB of signal-to-noise and distortion ratio (SNDR), 68 dB of signal-to-noise ratio (SNR), and 68.2 dB of dynamic range (DR) within 50.5 MHz of bandwidth (BW), while consuming 19 mW of total power (P). The proposed modulator features 161.5 dB of figure-of-merit (FOM), defined as FOM = SNDR + 10 log10 (BW/P)

High Speed Camera Chip

abstract: The market for high speed camera chips, or image sensors, has experienced rapid growth over the past decades owing to its broad application space in security, biomedical equipment, and mobile devices. CMOS (complementary metal-oxide-semiconductor) technology has significantly improved the performance of the high speed camera chip by enabling the monolithic integration of pixel circuits and on-chip analog-to-digital conversion. However, for low light intensity applications, many CMOS image sensors have a sub-optimum dynamic range, particularly in high speed operation. Thus the requirements for a sensor to have a high frame rate and high fill factor is attracting more attention. Another drawback for the high speed camera chip is its high power demands due to its high operating frequency. Therefore, a CMOS image sensor with high frame rate, high fill factor, high voltage range and low power is difficult to realize. This thesis presents the design of pixel circuit, the pixel array and column readout chain for a high speed camera chip. An integrated PN (positive-negative) junction photodiode and an accompanying ten transistor pixel circuit are implemented using a 0.18 µm CMOS technology. Multiple methods are applied to minimize the subthreshold currents, which is critical for low light detection. A layout sharing technique is used to increase the fill factor to 64.63%. Four programmable gain amplifiers (PGAs) and 10-bit pipeline analog-to-digital converters (ADCs) are added to complete on-chip analog to digital conversion. The simulation results of extracted circuit indicate ENOB (effective number of bits) is greater than 8 bits with FoM (figures of merit) =0.789. The minimum detectable voltage level is determined to be 470μV based on noise analysis. The total power consumption of PGA and ADC is 8.2mW for each conversion. The whole camera chip reaches 10508 frames per second (fps) at full resolution with 3.1mm x 3.4mm area.Dissertation/ThesisMasters Thesis Electrical Engineering 201