2 research outputs found
Non-Stationary Polar Codes for Resistive Memories
Resistive memories are considered a promising memory technology enabling high
storage densities with in-memory computing capabilities. However, the readout
reliability of resistive memories is impaired due to the inevitable existence
of wire resistance, resulting in the sneak path problem. Motivated by this
problem, we study polar coding over channels with different reliability levels,
termed non-stationary polar codes, and we propose a technique improving its bit
error rate (BER) performance. We then apply the framework of non-stationary
polar codes to the crossbar array and evaluate its BER performance under two
modeling approaches, namely binary symmetric channels (BSCs) and binary
asymmetric channels (BSCs). Finally, we propose a technique for biasing the
proportion of high-resistance states in the crossbar array and show its
advantage in reducing further the BER. Several simulations are carried out
using a SPICE-like simulator, exhibiting significant reduction in BER
Variability-Aware Read and Write Channel Models for 1S1R Crossbar Resistive Memory with High Wordline/Bitline Resistance
Crossbar resistive memory with 1 Selector 1 Resistor (1S1R) structure is
attractive for low-cost and high-density nonvolatile memory applications. As
technology scales down to the single-nm regime, the increasing resistivity of
wordline/bitline becomes a limiting factor to device reliability. This paper
presents write/read communication channels while considering the line
resistance and device variabilities by statistically relating the degraded
write/read margins and the channel parameters. Binary asymmetric channel (BAC)
models are proposed for the write/read operations and array capacity results
are presented. Simulations based on these models suggest that the bit-error
rate of devices are highly non-uniform across the memory array. These models
provide quantitative tools for evaluating the trade-offs between memory
reliability and design parameters, such as array size, technology nodes, and
aspect ratio, and also for designing coding-theoretic solutions that would be
most effective for crossbar memory