A novel deep submicron bulk planar sizing strategy for low energy subthreshold standard cell libraries

Engineering andPhysical Science ResearchCouncil (EPSRC) and Arm Ltd for providing funding in the form of grants and studentshipsThis work investigates bulk planar deep submicron semiconductor physics in an attempt to improve standard cell libraries aimed at operation in the subthreshold regime and in Ultra Wide Dynamic Voltage Scaling schemes. The current state of research in the field is examined, with particular emphasis on how subthreshold physical effects degrade robustness, variability and performance. How prevalent these physical effects are in a commercial 65nm library is then investigated by extensive modeling of a BSIM4.5 compact model. Three distinct sizing strategies emerge, cells of each strategy are laid out and post-layout parasitically extracted models simulated to determine the advantages/disadvantages of each. Full custom ring oscillators are designed and manufactured. Measured results reveal a close correlation with the simulated results, with frequency improvements of up to 2.75X/2.43X obs erved for RVT/LVT devices respectively. The experiment provides the first silicon evidence of the improvement capability of the Inverse Narrow Width Effect over a wide supply voltage range, as well as a mechanism of additional temperature stability in the subthreshold regime. A novel sizing strategy is proposed and pursued to determine whether it is able to produce a superior complex circuit design using a commercial digital synthesis flow. Two 128 bit AES cores are synthesized from the novel sizing strategy and compared against a third AES core synthesized from a state-of-the-art subthreshold standard cell library used by ARM. Results show improvements in energy-per-cycle of up to 27.3% and frequency improvements of up to 10.25X. The novel subthreshold sizing strategy proves superior over a temperature range of 0 °C to 85 °C with a nominal (20 °C) improvement in energy-per-cycle of 24% and frequency improvement of 8.65X. A comparison to prior art is then performed. Valid cases are presented where the proposed sizing strategy would be a candidate to produce superior subthreshold circuits

Impact of atomistic device variability on analogue circuit design

Scaling of complementary metal-oxide-semiconductor (CMOS) technology has benefited the semiconductor industry for almost half a century. For CMOS devices with a physical gate-length in the sub-100 nm range, extreme device variability is introduced and has become a major stumbling block for next generation analogue circuit design. Both opportunities and challenges have therefore confronted analogue circuit designers. Small geometry device can enable high-speed analogue circuit designs, such as data conversion interfaces that can work in the radio frequency range. These designs can be co-integrated with digital systems to achieve low cost, high-performance, single-chip solutions that could only be achieved using multi-chip solutions in the past. However, analogue circuit designs are extremely vulnerable to device mismatch, since a large number of symmetric transistor pairs and circuit cells are required. The increase in device variability from sub-100 nm processes has therefore significantly reduced the production yield of the conventional designs. Mismatch models have been developed to analytically evaluate the magnitude of random variations. Based on measurements from custom designed test structures, the statistics of process variation can be estimated using design related parameters. However, existing models can no longer accurately estimate the magnitude of mismatch for sub-100 nm “atomistic” devices, since short-channel effects have become important. In this thesis, a new mismatch model for small geometry devices will be proposed to address this problem. Based on knowledge of the matching performance obtained from the mismatch model, design solutions are desired at different design levels for a variety of circuit topologies. In this thesis, transistor level compensation solutions have been investigated and closed-loop compensation circuits have been proposed. At circuit level, a latch-based comparator has been used to develop a compensation solution because this type of comparator is extremely sensitive to the device mismatch. These comparators are also used as the fundamental building block for the analogue-to-digital converters (ADC). The proposed comparator compensation scheme is used to improve the performance of a high-speed flash ADC

Low Power SoC Design

The design of Low Power Systems-on-Chips (SoC) in very deep submicron technologies becomes a very complex task that has to bridge very high level system description with low-level considerations due to technology defaults and variations and increasing system and circuit complexity. This paper describes the major low-level issues, such as dynamic and static power consumption, temperature, technology variations, interconnect, DFM, reliability and yield, and their impact on high-level design, such as the design of multi-Vdd, fault-tolerant, redundant or adaptive chip architectures. Some very low power System-on-Chip (SoC) will be presented in three domains: wireless sensor networks, vision sensors and mobile TV

Nonlinear integrated photonics on silicon and gallium arsenide substrates

Silicon photonics is nowadays a mature technology and is on the verge of becoming a blossoming industry. Silicon photonics has also been pursued as a platform for integrated nonlinear optics based on Raman and Kerr effects. In recent years, more futuristic directions have been pursued by various groups. For instance, the realm of silicon photonics has been expanded beyond the well-established near-infrared wavelengths and into the mid-infrared (3 - 5 µm). In this wavelength range, the omnipresent hurdle of nonlinear silicon photonics in the telecommunication band, i.e., nonlinear losses due to two-photon absorption, is inherently nonexistent. With the lack of efficient light-emission capability and second-order optical nonlinearity in silicon, heterogeneous integration with other material systems has been another direction pursued. Finally, several approaches have been proposed and demonstrated to address the energy efficiency of silicon photonic devices in the near-infrared wavelength range. In this dissertation, theoretical and experimental works are conducted to extend applications of integrated photonics into mid-infrared wavelengths based on silicon, demonstrate heterogeneous integration of tantalum pentoxide and lithium niobate photonics on silicon substrates, and study two-photon photovoltaic effect in gallium arsenide and plasmonic-enhanced structures. Specifically, performance and noise properties of nonlinear silicon photonic devices, such as Raman lasers and optical parametric amplifiers, based on novel and reliable waveguide technologies are studied. Both near-infrared and mid-infrared nonlinear silicon devices have been studied for comparison. Novel tantalum-pentoxide- and lithium-niobate-on-silicon platforms are developed for compact microring resonators and Mach-Zehnder modulators. Third- and second-harmonic generations are theoretical studied based on these two platforms, respectively. Also, the two-photon photovoltaic effect is studied in gallium arsenide waveguides for the first time. The effect, which was first demonstrated in silicon, is the nonlinear equivalent of the photovoltaic effect of solar cells and offers a viable solution for achieving energy-efficient photonic devices. The measured power efficiency achieved in gallium arsenide is higher than that in silicon and even higher efficiency is theoretically predicted with optimized designs. Finally, plasmonic-enhanced photovoltaic power converters, based on the two-photon photovoltaic effect in silicon using subwavelength apertures in metallic films, are proposed and theoretically studied

Quantum Technology: The Second Quantum Revolution

We are currently in the midst of a second quantum revolution. The first quantum revolution gave us new rules that govern physical reality. The second quantum revolution will take these rules and use them to develop new technologies. In this review we discuss the principles upon which quantum technology is based and the tools required to develop it. We discuss a number of examples of research programs that could deliver quantum technologies in coming decades including; quantum information technology, quantum electromechanical systems, coherent quantum electronics, quantum optics and coherent matter technology.Comment: 24 pages and 6 figure

A microchip optomechanical accelerometer

The monitoring of accelerations is essential for a variety of applications ranging from inertial navigation to consumer electronics. The basic operation principle of an accelerometer is to measure the displacement of a flexibly mounted test mass; sensitive displacement measurement can be realized using capacitive, piezo-electric, tunnel-current, or optical methods. While optical readout provides superior displacement resolution and resilience to electromagnetic interference, current optical accelerometers either do not allow for chip-scale integration or require bulky test masses. Here we demonstrate an optomechanical accelerometer that employs ultra-sensitive all-optical displacement read-out using a planar photonic crystal cavity monolithically integrated with a nano-tethered test mass of high mechanical Q-factor. This device architecture allows for full on-chip integration and achieves a broadband acceleration resolution of 10 \mu g/rt-Hz, a bandwidth greater than 20 kHz, and a dynamic range of 50 dB with sub-milliwatt optical power requirements. Moreover, the nano-gram test masses used here allow for optomechanical back-action in the form of cooling or the optical spring effect, setting the stage for a new class of motional sensors.Comment: 16 pages, 9 figure

A novel low-swing voltage driver design and the analysis of its robustness to the effects of process variation and external disturbances

arket forces are continually demanding devices with increased functionality/unit area; these demands have been satisfied through aggressive technology scaling which, unfortunately, has impacted adversely on the global interconnect delay subsequently reducing system performance. Line drivers have been used to mitigate the problems with delay; however, these have a large power consumption. A solution to reducing the power dissipation of the drivers is to use lower supply voltages. However, by adopting a lower power supply voltage, the performance of the line drivers for global interconnects is impaired unless low-swing signalling techniques are implemented. Low-swing signalling techniques can provide high speed signalling with low power consumption and hence can be used to drive global on-chip interconnect. Most of the proposed low-swing signalling schemes are immune to noise as they have a good SNR. However, they tend to have a large penalty in area and complexity as they require additional circuitry such as voltage generators and low-Vth devices. Most of the schemes also incorporate multiple Vdd and reference voltages which increase the overall circuit complexity. A diode-connected driver circuit has the best attributes over other low-swing signalling techniques in terms of low power, low delay, good SNR and low area overhead. By incorporating a diode-connected configuration at the output, it can provide high speed signalling due to its high driving capability. However, this configuration also has its limitations as it has issues with its adaptability to process variations, as well as an issue with leakage currents. To address these limitations, two novel driver schemes have been designed, namely, nLVSD and mLVSD, which, additionally, have improvements in performance and power consumption. Comparisons between the proposed schemes with the existing diode-connected driver circuits (MJ and DDC) showed that the nLVSD and mLVSD drivers have approximately 46% and 50% less delay. The name MJ originates from the driver’s designer called Juan A. Montiel-Nelson, while DDC stands for dynamic diode-connected. In terms of power consumption, the nLVSD and mLVSD drivers also produce 43% and 7% improvement. Additionally, the mLVSD driver scheme is the most robust as its SNR is 14 to 44% higher compared to other diode-connected driver circuits. On the other hand, the nLVSD driver has 6% lower SNR compared to the MJ driver, even though it is 19% more robust than the DDC driver. However, since its SNR is still above 1, its improved performance and reduced power consumption, as well other advantages it has over other diode-connected driver circuits can compensate for this limitation. Regarding the robustness to external disturbances, the proposedmdriver circuits are more robust to crosstalk effects as the nLVSD and mLVSD drivers are approximately 35% and 7% more robust than other diode-connected drivers. Furthermore, the mLVSD driver is 5%, 33% and 47% more tolerant to SEUs compared to the nLVSD, MJ and DDC driver circuits respectively, whilst the MJ and DDC drivers are 26% and 40% less tolerant to SEUs iii compared to the nLVSD circuit. A comparison between the four schemes was also undertaken in the presence of ±3σ process and voltage (PV) variations. The analysis indicated that both proposed driver schemes are more robust than other diode-connected driver schemes, namely, the MJ and DDC driver circuits. The MJ driver scheme deviates approximately 18% and 35% more in delay and power consumption compared to the proposed schemes. The DDC driver has approximately 20% and 57% more variations in delay and power consumption in comparison to the proposed schemes. In order to further improve the robustness of the proposed driver circuits against process variation and environmental disturbances, they were further analysed to identify which process variables had the most impact on circuit delay and power consumption, as well as identifying several design techniques to mitigate problems with environmental disturbances. The most significant process parameters to have impact on circuit delay and power consumption were identified to be Vdd, tox, Vth, s, w and t. The impact of SEUs on the circuit can be reduced by increasing the bias currents whilst design methods such as increasing the interconnect spacing can help improve the circuit robustness against crosstalk. Overall it is considered that the proposed nLVSD and mLVSD circuits advance the state of the art in driver design for on-chip signalling applications.EThOS - Electronic Theses Online ServiceGBUnited Kingdo