2 research outputs found
Yield improvement of an electronic device
Tämä diplomityö perehtyy elektroniikkatuotteen valmistusprosessiin ja analysoi eri prosessivaiheiden vaikutuksia saantotasoon. Työssä selvitetään hylättyjen tuotteiden vikojen alkuperiä sekä haetaan parannuskeinoja vikojen eliminoimiseksi. Saannon tason nostaminen tuottaa säästöä sekä kustannuksissa että materiaaleissa ja raaka-aineissa.
Tutkimuksessa hyödynnettiin tilastollista tutkimusta, kustannuslaskentaa ja laadullista tutkimusta. Valmistusprosessissa olevien tarkastusten ja testausten saantotilastoja seurattiin tietokannasta, jonne tulokset tallentuivat. Tuotantoprosessissa käytettiin visuaalista tarkastusta sekä sähköistä testausta. Sähköisen testauksen luotettavuutta arvioitiin lisäksi Gage R&R-tutkimuksella. Hylättyjä tuotteita tutkittiin tarkemmin optisesti ja suurimmat hylkäyssyyt kohdennettiin valmistusprosessien eri vaiheisiin. Tämän jälkeen analysoitiin johtuivatko hylkäyssyyt nimenomaan kyseisen vaiheen prosessoinnista vai mahdollistiko prosessi vain vian ilmenemisen. Sen jälkeen prosessille kehitettiin parannusehdotus viallisten tuotteiden määrän eliminoimiseksi.
Suurimmiksi viallisten tuotteiden lähteeksi paljastuivat pinnoitusprosessit sekä anturin valmistuksen nystyttämis- ja etsausprosessit. Mikäli näiden prosessien aiheuttamat hylkäyssyyt saataisiin eliminoitua, hukasta aiheutuvia kustannuksia saataisiin alennettua huomattavasti. Esimerkin realistisilla laskelmilla hukkakustannuksia voidaan alentaa prosessiketjuissa jopa 70-80 %, mikäli suurimmat vikaantumisen juurisyyt saataisiin eliminoitua täysin.This thesis studies an assembly process of an electronic device in a production environment. The yield level of a manufacturing process is of great importance from the economical as well as from the ecological viewpoint to the producing company. By producing less faulty products and more functional products manufacturing costs are reduced and less waste is produced.
This study was conducted using statistical process control tools and qualitative and quantitative analysis of the faulty products. Visual inspection and electrical testing were parts of the production process, from which information about faulty products could be acquired. The yield levels as well as the causes for failing the tests and inspections were recorded into a database, where they could be retrieved for later investigations. The reasons for test failures were identified and connected to the process causing them. Afterwards suggestions for process improvements were created.
The processes causing largest shares of the faulty products, or “scrap”, were identified to be the coating processes, the mounting of the solder balls on to the wafer and sensor etching process. If these processes could be improved so that these largest root causes could be completely eliminated, considerable costs could be saved. Using a realistic calculation example the so-called scrap costs could be lowered by as much as 80 percent. However, more research and testing should be done before fully implementing new processes or process changes into the production line
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No-flow underfill flip chip assembly–an experimental and modeling analysis
In the flip-chip assembly process, no-flow underfill materials have a particular advantage over traditional underfill: the application and curing of the former can be undertaken before and during the reflow process. This advantage can be exploited to increase the flip-chip manufacturing throughput. However, adopting a no-flow underfill process may introduce reliability issues such as underfill entrapment, delamination at interfaces between underfill and other materials, and lower solder joint fatigue life. This paper presents an analysis on the assembly and the reliability of flip-chips with no-flow underfill. The methodology adopted in the work is a combination of experimental and computer-modeling methods. Two types of no-flow underfill materials have been used for the flip chips. The samples have been inspected with X-ray and scanning acoustic microscope inspection systems to find voids and other defects. Eleven samples for each type of underfill material have been subjected to thermal shock test and the number of cycles to failure for these flip chips have been found. In the computer modeling part of the work, a comprehensive parametric study has provided details on the relationship between the material properties and reliability, and on how underfill entrapment may affect the thermal–mechanical fatigue life of flip chips with no-flow underfill