572 research outputs found
A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes
This paper propose a decoder architecture for low-density parity-check
convolutional code (LDPCCC). Specifically, the LDPCCC is derived from a
quasi-cyclic (QC) LDPC block code. By making use of the quasi-cyclic structure,
the proposed LDPCCC decoder adopts a dynamic message storage in the memory and
uses a simple address controller. The decoder efficiently combines the memories
in the pipelining processors into a large memory block so as to take advantage
of the data-width of the embedded memory in a modern field-programmable gate
array (FPGA). A rate-5/6 QC-LDPCCC has been implemented on an Altera Stratix
FPGA. It achieves up to 2.0 Gb/s throughput with a clock frequency of 100 MHz.
Moreover, the decoder displays an excellent error performance of lower than
at a bit-energy-to-noise-power-spectral-density ratio () of
3.55 dB.Comment: accepted to IEEE Transactions on Circuits and Systems
Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders
Polar codes are a recently proposed family of provably capacity-achieving
error-correction codes that received a lot of attention. While their
theoretical properties render them interesting, their practicality compared to
other types of codes has not been thoroughly studied. Towards this end, in this
paper, we perform a comparison of polar decoders against LDPC and Turbo
decoders that are used in existing communications standards. More specifically,
we compare both the error-correction performance and the hardware efficiency of
the corresponding hardware implementations. This comparison enables us to
identify applications where polar codes are superior to existing
error-correction coding solutions as well as to determine the most promising
research direction in terms of the hardware implementation of polar decoders.Comment: Fixes small mistakes from the paper to appear in the proceedings of
IEEE WCNC 2017. Results were presented in the "Polar Coding in Wireless
Communications: Theory and Implementation" Worksho
Deriving Good LDPC Convolutional Codes from LDPC Block Codes
Low-density parity-check (LDPC) convolutional codes are capable of achieving
excellent performance with low encoding and decoding complexity. In this paper
we discuss several graph-cover-based methods for deriving families of
time-invariant and time-varying LDPC convolutional codes from LDPC block codes
and show how earlier proposed LDPC convolutional code constructions can be
presented within this framework. Some of the constructed convolutional codes
significantly outperform the underlying LDPC block codes. We investigate some
possible reasons for this "convolutional gain," and we also discuss the ---
mostly moderate --- decoder cost increase that is incurred by going from LDPC
block to LDPC convolutional codes.Comment: Submitted to IEEE Transactions on Information Theory, April 2010;
revised August 2010, revised November 2010 (essentially final version).
(Besides many small changes, the first and second revised versions contain
corrected entries in Tables I and II.
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