6 research outputs found

    Low-Complexity Context-Based Motion Compensation for VLBR Video Encoding

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    A significant improvement of block-based motion estimation strategies is presented, which provides fast computation and very low bitrate coding. For each block, a spatio-temporal context is defined based on nearest neighbors in the current and previous frames, and a prediction list is built. Then, the best matching vector within the list is chosen as an estimation of the block motion. Since coder and decoder are synchronous, only the index of the selected vector is needed at the decoder to reconstruct the motion field. To avoid the propagation of the error, an additional correction vector can be sent when prediction error exceeds a threshold. Furthermore, bitrate saving is achieved through an adaptive sorting of the prediction list of each block, which allows to reduce the entropy of the motion indexes. Tests demonstrate that the proposed method ensures a speed up over 1:200 as compared to full search, and a coding gain above 2, with a negligible loss of accuracy. This allows real-time implementation of VLBR software video coders on conventional PC platforms

    Adaptive Fast Search Block Motion Estimation In Video Compression

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    With the advancement of telecommunication technologies, such as internet, video conferencing and HDTV, we need an effective video compression technique. Motion estimation and motion compensation are the most complicated and time consuming part of any video coding technique. Motion estimation helps to reduce temporal redundancy that exists between successive video frames. The motion estimation part of any video codec should be such that, it can reduce computational complexity without having any effect on the quality of the video. The motion estimation process can be more efficient if we use spatial and temporal correlation between the blocks in a frame and between two consecutive frames. In this thesis, a new search method for block motion estimation in video has been presented that uses neighbouring blocks of current macro-block and the block in the previous frame having the same coordinates as that of current macro-block for prediction of motion vectors. In the proposed method we use the motion vectors of neighbouring blocks that are more likely to be helpful in the prediction process. By using these motion vectors a search centre is located, around which a search window is placed. In this thesis, we have introduced Sorted Search Method (SSM) algorithm for motion estimation and compared the performance with existing Block Based Motion Estimation (BBME) techniques. Different sorting search methods have been developed by taking different neighbours around the current macro - block and their performances are compared

    Motion estimation based frame rate conversion hardware designs

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    Frame Rate Up-Conversion (FRC) is the conversion of a lower frame rate video signal to a higher frame rate video signal. FRC algorithms using Motion Estimation (ME) obtain better quality results. Among the block matching ME algorithms, Full Search (FS) achieves the best performance since it searches all search locations in a given search range. However, its computational complexity, especially for the recently available High Definition (HD) video formats, is very high. Therefore, in this thesis, we proposed new ME algorithms for real-time processing of HD video and designed efficient hardware architectures for implementing these ME algorithms. These algorithms perform very close to FS by searching much fewer search locations than FS algorithm. We implemented the proposed hardware architectures in VHDL and mapped them to a Xilinx FPGA. ME for FRC requires finding the true motion among consecutive frames. In order to find the true motion, Vector Median Filter (VMF) is used to smooth the motion vector field obtained by block matching ME. However, VMFs are difficult to implement in real-time due to their high computational complexity. Therefore, in this thesis, we proposed several techniques to reduce the computational complexity of VMFs by using data reuse methodology and by exploiting the spatial correlations in the vector field. In addition, we designed an efficient VMF hardware including the computation reduction techniques exploiting the spatial correlations in the motion vector field. We implemented the proposed hardware architecture in Verilog and mapped it to a Xilinx FPGA. ME based FRC requires interpolation of frames using the motion vectors found by ME. Frame interpolation algorithms also have high computational complexity. Therefore, in this thesis, we proposed a low cost hardware architecture for real-time implementation of frame interpolation algorithms. The proposed hardware architecture is reconfigurable and it allows adaptive selection of frame interpolation algorithms for each Macroblock. We implemented the proposed hardware architecture in VHDL and mapped it to a low cost Xilinx FPGA

    A Variable Search Length Block Matching Algorithm for Motion Estimation

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    : A new fast search algorithm for block matching motion estimation is presented in this paper. The new algorithm, called the Adaptive Search Length (ASL) algorithm, allows the maximum number of searches for each block of the image to vary according to the difficulty in finding the optimum motion vector. The PSNR of the decoded images produced by a video coder operating with the ASL algorithm were compared with those produced by a coder operating with the full search block matching algorithm. The results presented show that, for a PSNR of within .25 dB of the full search PSNR, the ASL algorithm requires only 10 % of the searches required by the full search algorithm. 1. INTRODUCTION All modern standard video coding algorithms employ motion estimation to reduce the redundancy between successive frames of a video sequence. The method adopted to estimate the motion between frames is the block matching algorithm (BMA) [1]. For the full search BMA, a measure of the difference between ever..
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