A Comparative Review on ALU using CMOS and GDI techniques for Power Dissipation and Propagation Delay

Arithmetic and Logic Circuits are to be designed with less power, compact size, less propagation delay in this fast growing era of technology. Arithmetic operations are indispensable and the basic functions for any high speed low power applications like digital signal processing, microprocessors, image processing, etc. Consumption of power is the major issue in designing these circuits. Also the number of transistors required is also the one of the issues in designing the circuits. To minimize the transistors required in designing the circuits and to reduce the power consumption of the circuits, the authors have referred some techniques to overcome these problems in this paper. By reviewing all these techniques, the authors try to implement the GDI technique to reduce the power consumption and transistors count or the area required to design the circuits

Advanced analog layout design automation in compliance with density uniformity

To fabricate a reliable integrated circuit chip, foundries follow specific design rules and layout processing techniques. One of the parameters, which affect circuit performance and final electronic product quality, is the variation of thickness for each semiconductor layer within the fabricated chips. The thickness is closely dependent on the density of geometric features on that layer. Therefore, to ensure consistent thickness, foundries normally have to seriously control distribution of the feature density on each layer by using post-processing operations. In this research, the methods of controlling feature density distribution on different layers of an analog layout during the process of layout migration from an old technology to a new one or updated design specifications in the same technology have been investigated. We aim to achieve density-uniformity-aware layout retargeting for facilitating manufacturing process in the advanced technologies. This can offer an advantage right to the design stage for the designers to evaluate the effects of applying density uniformity to their drafted layouts, which are otherwise usually done by the foundries at the final manufacturing stage without considering circuit performance. Layout modification for density uniformity includes component position change and size modification, which may induce crosstalk noise caused by extra parasitic capacitance. To effectively control this effect, we have also investigated and proposed a simple yet accurate analytic method to model the parasitic capacitance on multi-layer VLSI chips. Supported by this capacitance modeling research, a unique methodology to deal with density-uniformity-aware analog layout retargeting with the capability of parasitic capacitance control has been presented. The proposed operations include layout geometry position rearrangement, interconnect size modification, and extra dummy fill insertion for enhancing layout density uniformity. All of these operations are holistically coordinated by a linear programming optimization scheme. The experimental results demonstrate the efficacy of the proposed methodology compared to the popular digital solutions in terms of minimum density variation and acute parasitic capacitance control

Analog layout design automation: ILP-based analog routers

The shrinking design window and high parasitic sensitivity in the advanced technology have imposed special challenges on the analog and radio frequency (RF) integrated circuit design. In this thesis, we propose a new methodology to address such a deficiency based on integer linear programming (ILP) but without compromising the capability of handling any special constraints for the analog routing problems. Distinct from the conventional methods, our algorithm utilizes adaptive resolutions for various routing regions. For a more congested region, a routing grid with higher resolution is employed, whereas a lower-resolution grid is adopted to a less crowded routing region. Moreover, we strengthen its speciality in handling interconnect width control so as to route the electrical nets based on analog constraints while considering proper interconnect width to address the acute interconnect parasitics, mismatch minimization, and electromigration effects simultaneously. In addition, to tackle the performance degradation due to layout dependent effects (LDEs) and take advantage of optical proximity correction (OPC) for resolution enhancement of subwavelength lithography, in this thesis we have also proposed an innovative LDE-aware analog layout migration scheme, which is equipped with our special routing methodology. The LDE constraints are first identified with aid of a special sensitivity analysis and then satisfied during the layout migration process. Afterwards the electrical nets are routed by an extended OPC-inclusive ILP-based analog router to improve the final layout image fidelity while the routability and analog constraints are respected in the meantime. The experimental results demonstrate the effectiveness and efficiency of our proposed methods in terms of both circuit performance and image quality compared to the previous works

Design and optimization of piezoelectric MEMS vibration energy harvesters

Low-power electronic applications are normally powered by batteries, which have to deal with stringent lifetime and size constraints. To enhance operational autonomy, energy harvesting from ambient vibration by micro-electromechanical systems (MEMS) has been identified as a promising solution to this universal problem. In this thesis, multiple configurations for MEMS-based piezoelectric energy harvesters are studied. To enhance their performances, automated design and optimization methodologies with minimum human efforts are proposed. Firstly, the analytic equations to estimate resonant frequency and amplitude of the harvested voltage for two different configurations of unimorph MEMS piezoelectric harvesters (i.e., with and without integration of a proof mass) are presented with their accuracy validated by using finite element method (FEM) simulation and prototype measurement. Thanks to their high accuracy, we use these analytic equations as fitness functions of genetic algorithm (GA), an evolutionary computation method for optimization problems by mimicking biological evolution. By leveraging the micro-fabrication process, we demonstrate that the GA can optimize the mechanical geometry of the prototyped harvester effectively and efficiently, whose peak harvested voltage increases from 310 mV to 1900 mV at the reduced resonant frequency from 886 Hz to 425 Hz with the highest normalized voltage density of 163.88 among the alternatives. With an intention of promoting uniform stress distribution along the piezoelectric cantilever and providing larger area for placing proof masses, in this thesis a T-shaped cantilever structure with two degrees-of-freedom (DOF) is proposed. Thanks to this special configuration, a considerable amount of stress/strain can be obtained from the tip part of the structure during the vibration, in addition to the anchor region. An analytic model for computing the frequency response of the proposed structure is derived, and the harvester performance is studied analytically, numerically and experimentally. The conventional MEMS energy harvesters can only generate voltage disadvantageously in a narrow bandwidth at higher frequencies. Therefore, in this thesis we further propose a piezoelectric MEMS harvester with the capability of vibrating in multiple DOF, whose operational bandwidth is enhanced by taking advantage of both multimodal and nonlinear mechanisms. The proposed harvester has a symmetric structure with a doubly-clamped configuration enclosing three proof masses in distinct locations. Thanks to the uniform mass distribution, the energy harvesting efficiency can be considerably enhanced. To determine the optimum geometry for the preferred nonlinear behavior, we have also used optimization methodology based on GA. The prototype measurements demonstrate that our proposed piezoelectric MEMS harvester is able to generate voltage at 227 Hz (the first mode), 261.8 Hz (the second mode), and 286 Hz (the third mode). When the device operates at its second mode frequency, nonlinear behavior can be obtained with extremely small magnitude of base excitation (i.e., 0.2 m/s²). Its normalized power density (NPD) of 595.12 (μW·cm⁻³·m⁻²·s⁴) is found to be superior to any previously reported piezoelectric MEMS harvesters in the literature. In this dissertation, we also propose a piezoelectric MEMS vibration energy harvester with the capability of oscillating at ultralow (i.e., less than 200 Hz) resonant frequency. The mechanical structure of the proposed harvester is comprised of a doubly clamped cantilever with a serpentine pattern associated with several discrete masses. In order to obtain the optimal physical aspects of the harvester and speed up the design process, we have utilized a deep neural network, as an artificial intelligence (AI) method. Firstly, the deep neural network was trained, and then this trained network was integrated with the GA to optimize the harvester geometry to enhance its performance in terms of both resonant frequency and generated voltage. Our numerical results confirm that the accuracy of the network in prediction is above 90%. As a result, by taking advantage of this efficient AI-based performance estimator, the GA is able to reduce the device resonant frequency from 169Hz to 110.5Hz and increase its efficiency on harvested voltage from 2.5V to 3.4V under 0.25g excitation. To improve both durability and energy conversion efficiency of the piezoelectric MEMS harvesters, we further propose a curve-shaped anchoring scheme in this thesis. A doubly clamped curve beam with a mass at its center is considered as an anchor, while a straight beam with proof mass is integrated to the center of this anchor. To assess the fatigue damage, which is actually critical to the micro-sized silicon-based piezoelectric harvesters, we have utilized the Coffin-Manson method and FEM to study the fatigue lifetime of the proposed geometry comprehensively. Our proposed piezoelectric harvester has been fabricated and its capability in harnessing the vibration energy has been examined numerically and experimentally. It is found that the harvested energy can be enlarged by a factor of 2.66, while this improvement is gained by the resonant frequency reduction and failure force magnitude enlargement, in comparison with the conventional geometry of the piezoelectric MEMS harvesters