Progress of analog-hybrid computation

Review of fast analog/hybrid computer systems, integrated operational amplifiers, electronic mode-control switches, digital attenuators, and packaging technique

Design of Power/Analog/Digital Systems Through Mixed-Level Simulations

In recent years the development of the applications in the field of telecommunications, data processing, control, renewable energy generation, consumer and automotive electronics determined the need for increasingly complex systems, also in shorter time to meet the growing market demand. The increasing complexity is mainly due to the mixed nature of these systems that must be developed to accommodate the new functionalities and to satisfy the more stringent performance requirements of the emerging applications. This means a more complex design and verification process. The key to managing the increased design complexity is a structured and integrated design methodology which allows the sharing of different circuit implementations that can be at transistor level and/or at a higher level (i.e.HDL languages).In order to expedite the mixed systems design process it is necessary to provide: an integrated design methodology; a suitable supporting tool able to manage the entire design process and design complexity and its successive verification.It is essential that the different system blocks (power, analog, digital), described at different level of abstraction, can be co-simulated in the same design context. This capability is referred to as mixed-level simulation.One of the objectives of this research is to design a mixed system application referred to the control of a coupled step-up dc-dc converter. This latter consists of a power stage designed at transistor-level, also including accurate power device models, and the analog controller implemented using VerilogA modules. Digital controllers are becoming very attractive in dc-dc converters for their programmability, ability to implement sophisticated control schemes, and ease of integration with other digital systems. Thus, in this dissertation it will be presented a detailed design of a Flash Analog-to-Digital Converter (ADC). The designed ADC provides medium-high resolution associated to high-speed performance. This makes it useful not only for the control application aforementioned but also for applications with huge requirements in terms of speed and signal bandwidth. The entire design flow of the overall system has been conducted in the Cadence Design Environment that also provides the ability to mixed-level simulations. Furthermore, the technology process used for the ADC design is the IHP BiCMOS 0.25 µm by using 50 GHz NPN HBT devices

Concepts for smart AD and DA converters

This thesis studies the `smart' concept for application to analog-to-digital and digital-to-analog converters. The smart concept aims at improving performance - in a wide sense - of AD/DA converters by adding on-chip intelligence to extract imperfections and to correct for them. As the smart concept can correct for certain imperfections, it can also enable the use of more efficient architectures, thus yielding an additional performance boost. Chapter 2 studies trends and expectations in converter design with respect to applications, circuit design and technology evolution. Problems and opportunities are identfied, and an overview of performance criteria is given. Chapter 3 introduces the smart concept that takes advantage of the expected opportunities (described in chapter 2) in order to solve the anticipated problems. Chapter 4 applies the smart concept to digital-to-analog converters. In the discussed example, the concept is applied to reduce the area of the analog core of a current-steering DAC. It is shown that a sub-binary variable-radix approach reduces the area of the current-source elements substantially (10x compared to state-of-the-art), while maintaining accuracy by a self-measurement and digital pre-correction scheme. Chapter 5 describes the chip implementation of the sub-binary variable-radix DAC and discusses the experimental results. The results confirm that the sub-binary variable-radix design can achieve the smallest published current-source-array area for the given accuracy (12bit). Chapter 6 applies the smart concept to analog-to-digital converters, with as main goal the improvement of the overall performance in terms of a widely used figure-of-merit. Open-loop circuitry and time interleaving are shown to be key to achieve high-speed low-power solutions. It is suggested to apply a smart approach to reduce the effect of the imperfections, unintentionally caused by these key factors. On high-level, a global picture of the smart solution is proposed that can solve the problems while still maintaining power-efficiency. Chapter 7 deals with the design of a 500MSps open-loop track-and-hold circuit. This circuit is used as a test case to demonstrate the proposed smart approaches. Experimental results are presented and compared against prior art. Though there are several limitations in the design and the measurement setup, the measured performance is comparable to existing state-of-the-art. Chapter 8 introduces the first calibration method that counteracts the accuracy issues of the open-loop track-and-hold. A description of the method is given, and the implementation of the detection algorithm and correction circuitry is discussed. The chapter concludes with experimental measurement results. Chapter 9 introduces the second calibration method that targets the accuracy issues of time-interleaved circuits, in this case a 2-channel version of the implemented track-and-hold. The detection method, processing algorithm and correction circuitry are analyzed and their implementation is explained. Experimental results verify the usefulness of the method

Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications

As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced. This warrants more interest in analog-to-digital converter (ADC)-based serial link receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) relative to binary or mixed-signal receivers. Utilizing this back-end DSP allows for complex digital equalization and more bandwidth-efficient modulation schemes, while also displaying reduced process/voltage/temperature (PVT) sensitivity. Furthermore, these architectures offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes. However, the power consumption of the ADC front-end and subsequent digital signal processing is a major issue. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-effcient receiver. This dissertation presents efficient implementations for multi-GS/s time-interleaved ADCs with partial embedded equalization. First prototype details a 6b 1.6GS/s ADC with a novel embedded redundant-cycle 1-tap DFE structure in 90nm CMOS. The other two prototypes explain more complex 6b 10GS/s ADCs with efficiently embedded feed-forward equalization (FFE) and decision feedback equalization (DFE) in 65nm CMOS. Leveraging a time-interleaved successive approximation ADC architecture, new structures for embedded DFE and FFE are proposed with low power/area overhead. Measurement results over FR4 channels verify the effectiveness of proposed embedded equalization schemes. The comparison of fabricated prototypes against state-of-the-art general-purpose ADCs at similar speed/resolution range shows comparable performances, while the proposed architectures include embedded equalization as well

Reports on Hybrid-computer Hardware

Hybrid computer and differential analyzer design and development for university instruction progra

Low-power switched capacitor voltage reference

Low-power analog design represents a developing technological trend as it emerges from a rather limited range of applications to a much wider arena affecting mainstream market segments. It especially affects portable electronics with respect to battery life, performance, and physical size. Meanwhile, low-power analog design enables technologies such as sensor networks and RFID. Research opportunities abound to exploit the potential of low power analog design, apply low-power to established fields, and explore new applications. The goal of this effort is to design a low-power reference circuit that delivers an accurate reference with very minimal power consumption. The circuit and device level low-power design techniques are suitable for a wide range of applications. To meet this goal, switched capacitor bandgap architecture was chosen. It is the most suitable for developing a systematic, and groundup, low-power design approach. In addition, the low-power analog cell library developed would facilitate building a more complex low-power system. A low-power switched capacitor bandgap was designed, fabricated, and fully tested. The bandgap generates a stable 0.6-V reference voltage, in both the discrete-time and continuous-time domain. The system was thoroughly tested and individual building blocks were characterized. The reference voltage is temperature stable, with less than a 100 ppm/°C drift, over a --60 dB power supply rejection, and below a 1 [Mu]A total supply current (excluding optional track-and-hold). Besides using it as a voltage reference, potential applications are also described using derivatives of this switched capacitor bandgap, specifically supply supervisory and on-chip thermal regulation

Design of a low power switched-capacitor pipeline analog-to-digital converter

An Analog to Digital Converter (ADC) is a circuit which converts an analog signal into digital signal. Real world is analog, and the data processed by the computer or by other signal processing systems is digital. Therefore, the need for ADCs is obvious. In this thesis, several novel designs used to improve ADCs operation speed and reduce ADC power consumption are proposed. First, a high speed switched source follower (SSF) sample and hold amplifier without feedthrough penalty is implemented and simulated. The SSF sample and hold amplifier can achieve 6 Bit resolution with sampling rate at 10Gs/s. Second, a novel rail-to-rail time domain comparator used in successive approximation register ADC (SAR ADC) is implemented and simulated. The simulation results show that the proposed SAR ADC can only consume 1.3 muW with a 0.7 V power supply. Finally, a prototype pipeline ADC is implemented and fabricated in an IBM 90nm CMOS process. The proposed design is validated using measurement on a fabricated silicon IC, and the proposed 10-bit ADC achieves a peak signal-to-noise- and-distortion-ratio (SNDR) of 47 dB. This SNDR translates to a figure of merit (FOM) of 2.6N/conversion-step with a 1.2 V power supply

Simulation and Design of an UWB Imaging System for Breast Cancer Detection

Breast cancer is the most frequently diagnosed cancer among women. In recent years, the mortality rate due to this disease is greatly decreased thanks to both enormous progress in cancer research, and screening campaigns which have allowed the increase in the number of early diagnoses of the disease. In fact, if the tumor is identied in its early stage, e.g. when it has a diameter of less than one centimeter, the possibility of a cure can reach 93%. However, statistics show that more young aged women are suered breast cancer. The goal of screening exams for early breast cancer detection is to nd cancers before they start to cause symptoms. Regular mass screening of all women at risk is a good option to achieve that. Instead of meeting very high diagnostic standards, it is expected to yield an early warning, not a denitive diagnosis. In the last decades, X-ray mammography is the most ecient screening technique. However, it uses ionizing radiation and, therefore, should not be used for frequent check-ups. Besides, it requires signicant breast compression, which is often painful. In this scenario many alternative technologies were developed to overcome the limitations of mammography. Among these possibilities, Magnetic Resonance Imaging (MRI) is too expensive and time-consuming, Ultrasound is considered to be too operatordependent and low specicity, which are not suitable for mass screening. Microwave imaging techniques, especially Ultra WideBand (UWB) radar imaging, is the most interesting one. The reason of this interest relies on the fact that microwaves are non-ionizing thus permitting frequent examinations. Moreover, it is potentially lowcost and more ecient for young women. Since it has been demonstrated in the literatures that the dielectric constants between cancerous and healthy tissues are quite dierent, the technique consists in illuminating these biological tissues with microwave radiations by one or more antennas and analyzing the re ected signals. An UWB imaging system consists of transmitters, receivers and antennas for the RF part, the transmission channel and of a digital backend imaging unit for processing the received signals. When an UWB pulse strikes the breast, the pulse is re ected due to the dielectric discontinuity in tissues, the bigger the dierence, the bigger the backscatter. The re ected signals are acquired and processed to create the energy maps. This thesis aims to develop an UWB system at high resolution for the detection of carcinoma breast already in its initial phase. To favor the adoption of this method in screening campaigns, it is necessary to replace the expensive and bulky RF instrumentation used so far with ad-hoc designed circuits and systems. In order to realize that, at the very beginning, the overall system environment must be built and veried, which mainly consists of the transmission channel{the breast model and the imaging unit. The used transmission channel data come from MRI of the prone patient. In order to correctly use this numerical model, a simulator was built, which was implemented in Matlab, according to the Finite-Dierence-Time- Domain (FDTD) method. FDTD algorithm solves the electric and magnetic eld both in time and in space, thus, simulates the propagation of electromagnetic waves in the breast model. To better understand the eect of the system non-idealities, two 2D breast models are investigated, one is homogeneous, the other is heterogeneous. Moreover, the modeling takes into account all critical aspects, including stability and medium dispersion. Given the types of tissues under examination, the frequency dependence of tissue dielectric properties is incorporated into wideband FDTD simulations using Debye dispersion parameters. A performed further study is in the implementation of the boundary conditions. The Convolution Perfectly Matched Layer (CPML) is used to implement the absorbing boundaries. The objective of the imaging unit is to obtain an energy map representing the amount of energy re ected from each point of the breast, by recombining the sampled backscattered signals. For this purpose, the study has been carried out on various beamforming in the literature. The basic idea is called as "delay and sum", which is to align the received signals in such a way as to focus a given point in space and then add up all the contributions, so as to obtain a constructive interference at that point if this is a diseased tissue. In this work, Microwave Imaging via Space Time (MIST) Beamforming algorithm is applied, which is based on the above principle and add more elaborations of the signals in order to make the algorithm less sensitive to propagation phenomena in the medium and to the non-idealities of the system. It is divided into two distinct steps: the rst step, called SKin Artifact Removal (SKAR), takes care of removing the contributions from the signal caused by the direct path between the transmitter and receiver, the re ection of skin, as they are orders of magnitude higher compared to the re ections caused by cancers; the second step, which is BEAmForming (BEAF), performs the algorithm of reconstruction by forming a weighted combination of time delayed version of the calibrated re ected signals. As discussed above, more attention must be paid on the implementation of the ad-hoc integration circuits. In this scenario, due to the strict requirements on the RF receiver component, two dierent approaches of the implementation of the RF front-end, Direct Conversion (DC) receiver and Coherent Equivalent Time Sampling (CETS) receiver are compared. They are modeled behaviorally and the eects of various impairments, such as thermal, jitter, and phase noise, as well as phase inaccuracies, non-linearity, ADC quantization noise and distortion, on energy maps and on quantitative metrics such as SCR and SMR are evaluated. Dierential Gaussian pulse is chosen as the exciting source. Results show that DC receiver performs higher sensitivity to phase inaccuracies, which makes it less robust than the CETS receiver. Another advantage of the CETS receiver is that it can work in time domain with UWB pulses, other than in frequency domain with stepped frequency continuous waves like the DC one, which reduces the acquisition time without impacting the performance. Based on the results of the behavioral simulations, low noise amplier (LNA) and Track and Hold Amplier (THA) can be regarded as the most critical parts for the proposed CETS receiver, as well as the UWB antenna. This work therefore focuses on their hardware implementations. The LNA, which shows critical performance limitation at bandwidth and noise gure of receiver, has been developed based on common-gate conguration. And the THA based on Switched Source Follower (SSF) scheme has been presented and improved to obtain high input bandwidth, high sampling rate, high linearity and low power consumption. LNA and THA are implemented in CMOS 130nm technology and the circuit performance evaluation has been taken place separately and together. The small size UWB wide-slot antenna is designed and simulated in HFSS. Finally, in order to evaluate the eect of the implemented transistor level components on system performance, a multi-resolution top-down system methodology is applied. Therfore, the entire ow is analyzed for dierent levels of the RF frontend. Initially the system components are described behaviorally as ideal elements. The main activity consists in the analysis and development of the entire frontend system, observing and complementing each other blocks in a single ow simulation, clear and well-dened in its various interfaces. To achieve that the receiver is modeled and analyzed using VHDL-AMS language block by block, moreover, the impact of quantization, noise, jitter, and non-linearity is also evaluated. At last, the behavioral description of antenna, LNA and THA is replaced with a circuit-level one without changing the rest of the system, which permits a system-level assessment of low-level issues

A built-in self-test technique for high speed analog-to-digital converters

Fundação para a Ciência e a Tecnologia (FCT) - PhD grant (SFRH/BD/62568/2009