Nanocompilation for the Cell Matrix Architecture

The Cell Matrix Architecture is a massive array of dynamically self-configurable, uniformly connected, identical computational units. This architecture can enable efficient, practical and powerful evolvable computing on the scale of quadrillions of logic gates. Nanotechnology manufacturing techniques likely will be necessary to produce a device at this scale in the future, with current Cell Matrix research focused on simulation at the circuit layout and switch level. This paper reports on a technique for Nanocompilation, the automatic compilation for such molecular-scale architectures, of high level programming language instructions into a functional Cell Matrix configuration. The focus of this work is on control structures, such as loops and decision statements, memory systems and arithmetic units, which are necessary components of any computer program. The framework of this compiler approach is presented, along with examples of generated circuits, a discussion of design issues, and results of an experimental evaluation

Abstract- The Cell Matrix Architecture is a massive array

of dynamically self-configurable, uniformly connected, identical computational units. This architecture can enable efficient, practical and powerful evolvable computing on the scale of quadrillions of logic gates. Nanotechnology manufacturing techniques likely will be necessary to produce a device at this scale in the future, with current Cell Matrix research focused on simulation at the circuit layout and switch level. This paper reports on a technique for Nanocompilation, the automatic compilation for such molecular-scale architectures, of high level programming language instructions into a functional Cell Matrix configuration. The focus of this work is on control structures, such as loops and decision statements, memory systems and arithmetic units, which are necessary components of any computer program. The framework of this compiler approach is presented, along with examples of generated circuits, a discussion of design issues, and results of an experimental evaluation