DESIGN OF EFFICIENT NANOELECTRONIC MEMORY AND CRYPTOGRAPHIC CIRCUITS

This thesis presents the design of Nanoelectronic Memory cell and arrays compatible with molecular switch (nanodevice) electrical characteristics. The proposed transmission gate based CMOL (hybrid CMOS / Molecular) memory cell surmounts the operational difficulties facing previous design. The Control circuitry with improved multiplexer design is introduced in this dissertation. Yield improvement through replacing the defective cell with a free cell can be achieved using a proposed algorithm. Moreover, the proposed memory cell has the same area as the existing CMOL inverter cells allowing easier implementation of both logic and memory circuits on the same chip. An efficient hardware implementation of the SBox from the Advanced Encryption Standard (AES) is presented in this dissertation. Modification of the design was achieved by adding Tri­ state Inverter followed by an Inverter (TII). Simulation results show a reduction in the average power dissipation as well as the time delays. Reduction of supply voltage and using low Vdd in non critical path improved the performance by reducing the energy delay product. Different transistors models with dual threshold voltage (Vt) based on 65nm CMOS technology were applied to the design to achieve further improvement. Keywords: CMOL, CMOL circuits, Nanoscale memory, Control Circuit, AES, SBox, Deep sub-micron CMOS technology, Tri-state Inverter, Low Power SBo

NanoCMOS-Molecular Realization of Rijndael

Abstract. This paper describes the implementation of the Advanced Encryption Standard Algorithm, Rijndael, in a new nanoscale technology, called CMOL. This technology consists of an array of conventional CMOS gates and a wiring network, which consists of a high density mesh of nanowires. The basic Modules of Rijndael were implemented using CMOL architecture. It is observed that the implementation in such a technology has considerable advantages compared to a conventional CMOS approach as regards to defect tolerance, speed, area and power consumption