NBTI Lifetime Evaluation and Extension in Instruction Caches

CMOS devices suffer from wearout mechanismsresulting in reliability issues. Negative bias temperature instability(NBTI) is one of the dominant ageing effects that cancause threshold voltage shift on PMOS devices and subsequentlyimpact circuit performance. The static noise margin (SNM) of anSRAM cell may be sharply reduced with unbalanced NBTI stress.This will impact SRAM read stability. From our observationsof instruction caches, NBTI stress duty cycles for each cacheline generally have similar but unbalanced patterns even whenrunning very different programs. Based on the patterns, wepropose an algorithm to evaluate the lifetime of instructioncaches by running SPICE simulation. The results predict 6and 7 years NBTI lifetimes of instruction caches for ARM andMIPS architectures respectively. One of the practical solutionsis periodically flipping each cell to balance the degradation rate.However the performance benefits in terms of lifetime are notactually proven before. Using the stress patterns and lifetimeevaluation algorithm, our work for the first time prove thistechnique can extend the lifetime of the cache by two ordersof magnitude