Using carry-save adders in low-power multiplier blocks

For a simple multiplier block FIR filter design, we compare the effects on power consumption of using direct versus transposed direct forms, tree versus linear structures and carry-save (CS) versus carry-ripple (CR) adders (for which multiplier block algorithms have been designed). We find that tree structures offer power savings, as expected, as does transposition in general but not always. Selective use of CS adders is shown to offer power savings provided that care is taken with their deployment. Our best result is with a direct form CWCS hybrid. The need for new multiplier-block design algorithms is identified

Design guidelines for reconfigurable multiplier blocks

The newly proposed reconfigurable multiplier blocks offer significant savings in area over the traditional multiplier blocks for time-multiplexed digital filters or any other system where only a subset of the coefficients that can be produced by the multiplier block is needed in a given time. The basic structure comprises a multiplexer connected to at least one input of an adder/subtractor that can generate several partial products, leading to better area utilization. The multiplier block algorithm complexity of a design increases logarithmically as the number of the multiplexers is increased. Design guidelines for the maximum utilization of the reconfigurable multiplier block structures are also presented

A Focal-Plane Image Processor for Low Power Adaptive Capture and Analysis of the Visual Stimulus

Portable applications of artificial vision are limited by the fact that conventional processing schemes fail to meet the specifications under a tight power budget. A bio-inspired approach, based in the goal-directed organization of sensory organs found in nature, has been employed to implement a focal-plane image processor for low power vision applications. The prototype contains a multi-layered CNN structure concurrent with 32times32 photosensors with locally programmable integration time for adaptive image capture with on-chip local and global adaptation mechanisms. A more robust and linear multiplier block has been employed to reduce irregular analog wave propagation ought to asymmetric synapses. The predicted computing power per power consumption, 142MOPS/mW, is orders of magnitude above what rendered by conventional architectures

Inference on the tail process with application to financial time series modelling

To draw inference on serial extremal dependence within heavy-tailed Markov chains, Drees, Segers and Warcho{\l} [Extremes (2015) 18, 369--402] proposed nonparametric estimators of the spectral tail process. The methodology can be extended to the more general setting of a stationary, regularly varying time series. The large-sample distribution of the estimators is derived via empirical process theory for cluster functionals. The finite-sample performance of these estimators is evaluated via Monte Carlo simulations. Moreover, two different bootstrap schemes are employed which yield confidence intervals for the pre-asymptotic spectral tail process: the stationary bootstrap and the multiplier block bootstrap. The estimators are applied to stock price data to study the persistence of positive and negative shocks.Comment: 22 page

On the Implementation of Efficient Channel Filters for Wideband Receivers by Optimizing Common Subexpression Elimination Methods

No abstract availabl

Towards AER VITE: building spike gate signal

Neuromorphic engineers aim to mimic the precise and efficient mechanisms of the nervous system to process information using spikes from sensors to actuators. There are many available works that sense and process information in a spike-based way. But there are still several gaps in the actuation and motor control field in a spike-based way. Spike-based Proportional-Integrative-Derivative controllers (PID) are present in the literature. On the other hand, neuro-inspired control models as VITE (Vector Integration To End point) and FLETE (Factorization of muscle Length and muscle Tension) are also present in the literature. This paper presents another step toward the spike implementation of those neuro-inspired models. We present a spike-based ramp multiplier. VITE algorithm generates the way to achieve a final position targeted by a mobile robotic arm. The block presented is used as a gate for the way involved and it also puts the incoming movement on speed with a variable slope profile. Only spikes for information representation were used and the process is in real time. The software simulation based on Simulink and Xilinx System Generator shows the accurate adjust to the traditional processing for short time periods and the hardware tests confirm and extend the previous simulated results for any time. We have implemented the spikes generator, the ramp multiplier and the low pass filter into the Virtex-5 FPGA and connected this with an USB-AER (Address Event Representation) board to monitor the spikes.Ministerio de Ciencia e Innovación TEC2009-10639-C04-0

On the design and efficient implementation of the Farrow structure

This letter proposes an efficient implementation of the Farrow structure using sum-of-powers-of-two (SOPOT) coefficients and multiplier-block (MB). In particular, a novel algorithm for designing the Farrow coefficients in SOPOT form is detailed. Using the SOPOT coefficient representation, coefficient multiplication can be implemented with limited number of shifts and additions. Using MB, the redundancy between multipliers can be fully exploited through the reuse of the intermediate results generated. Design examples show that the proposed method can greatly reduce the complexity of the Farrow structure while providing comparable phase and amplitude responses.published_or_final_versio