Multilayer Layer Graphene Nanoribbon Flash Memory: Analysis of Programming and Erasing Operation

Flash memory based on floating gate transistor is the most widely used memory technology in modern microelectronic applications. We recently proposed a new concept of multilayer graphene nanoribbon (MLGNR) and carbon nanotube (CNT) based floating gate transistor design for future nanoscale flash memory technology. In this paper, we analyze the tunneling current mechanism in the proposed graphene-CNT floating gate transistor. We anticipate that the proposed floating gate transistor would adopt Fowler-Nordheim (FN) tunneling during its programming and erase operations. In this paper, we have investigated the mechanism of tunneling current and the factors that would influence this current and the behavior of the proposed floating gate transistor. The analysis reveals that FN tunneling is a strong function of the high field induced by the control gate, and the thicknesses of the control oxide and the tunnel oxide.Comment: in IEEE SOCC, Las Vegas, USA, 201

Graphene Nanotechnology the Next Generation Logic, Memory and 3D Integrated Circuits

Title from PDF of title page viewed August 28, 2017Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 120-136)Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2016Floating gate transistor is the basic building block of non-volatile flash memory, which is one of the most widely used memory gadgets in modern micro and nano electronic applications. Recently there has been a surge of interest to introduce a new generation of memory devices using graphene nanotechnology. In this paper we present a new floating gate transistor (FGT) design based on multilayer graphene nanoribbon (MLGNR) and carbon nanotube (CNT). In the proposed graphene based floating gate transistor (GFGT) a multilayer structure of graphene nanoribbon (GNR) would be used as the channel of the field effect transistor (FET) and a layer of CNTs would be used as the floating gate. We have performed an analysis of the charge accumulation mechanism in the floating gate and its dependence on the applied terminal voltages. Based on our analysis we have observed that proposed graphene based floating gate transistor could be operated at a reduced voltage compared to conventional silicon based floating gate devices. We have presented detail analysis of the operation and the programming and erasing processes of the proposed FGT, dependency of the programming and erasing current density on different parameters, impact of scaling the thicknesses of the control and tunneling oxides. These analyses are done based on the equivalent capacitance model of the device. We have analyze the programming and erasing by the tunneling current mechanism in the proposed graphene-CNT floating gate transistor. In this paper, we have investigated the mechanism of programming current and the factors that would influence this current and the behavior of the proposed floating gate transistor. The analysis reveals that programming is a strong function of the high field induced by the control gate, and the thicknesses of the control oxide and the tunnel oxide. With the growing demand for nonvolatile flash memory devices and increasing limitations of silicon technologies, there has been a growing interest to develop emerging flash memory by using alternative nanotechnology. The proposed FGT device for nonvolatile flash memory contains an MLGNR channel and a CNT floating gate with SiO₂ as the tunnel oxide. In this paper, we have presented detail analysis of the electrical properties and performance characteristics of the proposed FGT device. We have focused on the following aspects: current voltage (I-V) characteristics, threshold voltage variation (∆VTH), programming, erasing and reading power consumptions compared to the existing FGTs, and layer-by-layer current voltage characteristics comparison of the proposed GFGT device. To realize graphene field effect transistor (GFET), a general model is developed, validated and analyzed. This model is also used to estimate graphene channel behavior of the proposed GFGT. Reliability is the major concern of the Flash memory technology. We have analyzed retention characteristics of the proposed GFGT. We also have developed a radiation harness test model for the Si-FGT by using VTH variation principle due to the radiation exposure. Flash memory experiences adverse effects due to radiation. These effects can be raised in terms of doping, feature size, supply voltages, layout, shielding. The operating point shift of the device forced to enter the logically-undefined region and cause upset and data errors under radiation exposure. In this research, the threshold voltage shift of the floating gate transistor (FGT) is analyzed by a mathematical model. Molybdenum disulfide (MoS2) based field effect transistor is considered as one of the promising future logic devices. Many other nanoelectronic devices based on MoS2 are currently under investigation. However, the challenge of providing reliable and efficient contact between 2D materials like MoS2 and the metal is still unresolved. The contact resistance between metal and MoS2 limits the application of MoS2 in current semiconductor technologies. In this paper, a detail analysis of metal-MoS2 contact has been presented. Specific contributions of this work are:investigation of the physical, material and electrical parameters that would determine the contact properties, analysis of the combined impact of the top and back gates for the first time, modeling of the crucial metal-MoS2 contact parameters, such as, sheet resistance (RSh), contact resistivity (ρc), contact resistance (RC) and transfer length (LT), investigation of the ways to incorporate the developed contact model into the electronic design automation (EDA) tools and investigation of different contact materials for the metal-MoS2 contact. The three dimensional integrated circuit (3D- IC) is expected to extend Moore's law. To reduce interconnects and time delay, semiconductor industry is shifting 2D-IC to 2.5D-IC and 3D-IC. 3D-IC is the ultimate goal of the semiconductor industry, where 2.5D-IC is an intermediate state. It is important to realize CAD design challenges of the 2.5D-IC/3D-IC when minimum spacing interconnects are used. The major contributions of this research work are as follows. Previously, for the small scale experimental purpose, small numbers (10-20) of TSVs, interconnects, bumps are fabricated together by hand calculation. However in the real 3D-IC design, thousands of TSVs, interconnects, bumps are reuired. Therefore, an automated CAD solution is required to provide precise physical design and verification. Therefore, a solid CAD solution is provided here. Compatible with 40nm-technology design, which enables the Silicon Interposer to integrate with the digital, analog and RF dies together. Dimensions and spacing of the TSV and Bump are optimized by the 3D EM full wave field solver. To our best knowledge, at the interposer level, this design reports the most dense and well-defined RDL, TSV and micro-bump co-design on Silicon Interposer, which will be used for 2.5D-IC.Introduction and background -- Proposed Graphene Based Flash Memory -- Physical and Electrical Parameters of the Proposed Graphene Flash Memory Device -- Programming and Erasing Operation of the Proposed Graphene Flash Memory Device -- Reliability Analysis of the Proposed Graphene Flash Memory Device -- Radiation Hardness Analysis of the Floating Gate Transistor -- Benchmarking of the Proposed Graphene Flash Memory Device -- Graphene Field Effect Transistor (GFET) Generalized Model -- MoS2 FET Device and Contact Characterization and Modelling based on Modified Transfer Length Method (TLM) -- 2.5D Silicon Interposer Design in 40nm-Technology for 2D-IC and 3D-IC -- Conclusion and Future Wor

신축성 있고 착용 가능한 탄소 나노튜브 기반 전자 기술

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 협동과정 바이오엔지니어링전공, 2020. 8. 김대형.Networks of carbon nanotubes (CNTs) are a promising candidate for use as a basic building block for next-generation soft electronics, owing to their superior mechanical and electrical properties, chemical stability, and low production cost. In particular, the CNTs, which are produced as a mixture of metallic and semiconducting CNTs via chemical vapor deposition, can be sorted according to their electronic types, which makes them useful for specific purposes: semiconducting CNTs can be employed as channel materials in transistor-based applications and metallic CNTs as electrodes. However, the development of CNT-based electronics for soft applications is still at its infant stage, mainly limited by the lack of solid technologies for developing high-performance deformable devices whose electrical performances are comparable to those fabricated using conventional inorganic materials. In this regard, soft CNT electronics with high mechanical stability and electrical performances have been pursued. First, wearable nonvolatile memory modules and logic gates were fabricated by employing networks of semiconducting CNTs as the channel materials, with strain-tolerant device designs for high mechanical stability. The fabricated devices exhibited low operation voltages, high device-to-device uniformity, on/off ratios, and on-current density, while maintaining its performance during ~30% stretching after being mounted on the human skin. In addition, various functional logic gates verified the fidelity of the reported technology, and successful fabrication of non-volatile memory modules with wearable features has been reported for the first time at the time of publication. Second, the networks of semiconducting CNTs were used to fabricate signal amplifiers with a high gain of ~80, which were then used to amplify electrocardiogram (ECG) signals measured using a wearable sensor. At the same time, color-tunable organic light-emitting diodes (CTOLEDs) were developed based on ultra-thin charge blocking layer that controlled the flow of excitons during different voltage regimes. Together, they were integrated to construct a health monitoring platform whereby real-time ECG signals could be detected while simultaneously notifying its user of the ECG status via color changes of the wearable CTOLEDs. Third, intrinsically stretchable CNT transistors were developed, which was enabled by the developments of thickness controllable, vacuum-deposited stretchable dielectric layer and vacuum-deposited metal thin films. Previous works employed strain-tolerant device designs which are based on the use of filamentary serpentine-shaped interconnections, which severely sacrifice the device density. The developed stretchable dielectric, compatible with the current vacuum-based microfabrication technology, exhibited excellent insulating properties even for nanometer-range thicknesses, thereby enabling significant electrical performance improvements such as low operation voltage and high device uniformity/reproducibility, which has not been realized in the most advanced intrinsically stretchable transistors of today.탄소 나노튜브는 뛰어난 전기적, 화학적, 그리고 기계적 특성을 갖고 있어 차세대 유연 전자소자의 핵심 소재 중 하나로 각광을 받고 있으나, 아직까지 이를 이용한 실용적인 유연 전자소자의 개발은 실현되지 않고 있다. 이는 탄소 나노튜브의 전기적 특성대로 완벽히 분류해 낼 수 있는 기술, 탄소 나노튜브를 소자의 원하는 위치에 정확히 원하는 양만큼 네트워크 형태 혹은 정렬된 형태로 증착하는 기술, 그리고 유연 전자소자를 구성하는 다른 물질들의 개발 기술의 부재 때문이다. 지난 10여년간 해당 기술들은 광범위하게 연구되어지고 있으나, 탄소 나노튜브를 활용한 우수한 유연 전자소자 개발을 위한 핵심 기술들의 발전은 아직 초기 단계에 있다. 따라서 이 논문을 통해 탄소 나노튜브를 유연 전자소자에 적용시킬 수 있는 새로운 기술을 소개하고자 한다. 첫번째로 탄소 나노튜브와 유연 전자소자의 소자 디자인을 이용하여 피부위에 증착 가능한 비휘발성 메모리 소자를 제작하였고, 해당 기술을 이용하여 피부위에서 안전하게 동작할 수 있는 다양한 기초 회로들을 구현하였다. 탄소 나노튜브 기반 메모리 전자 소자 및 회로는 다양한 외부 응력이 가해져도 안정적으로 동작을 하였고, 개발된 기술을 통해 보다 실용적인 탄소 나노튜브 기반 유연 전자 소자의 제작 조건을 확립할 수 있었다. 두번째로 위에 개발된 기술을 바탕으로, 보다 복잡한 탄소 나노튜브 기반 유연 회로 및 구동전압에 따라 발광색이 변환하는 색변환 소자를 제작하여 해당 소자들이 피부위에 부착되어 잘 작동되도록 구현하였다. 그리고 이 두 가지 웨어러블 전자소자를 통합하여 실시간으로 심전도를 측정하여 탄소 나노튜브 기반 전자소자를 통해 해당 신호를 증폭시키고, 신호의 상태를 색변환 소자로 나타낼 수 있는 심전도 모니터 시스템을 구현하였다. 세번째로 진공 증착이 가능한 유연 절연체를 개발하여, 기존의 유연 전자소자들이 가지고 있던 극명한 한계를 극복하였다 (높은 구동 전압, 낮은 집적도, 대면적 소자 선능 균일도 등). 기존의 액상 기반 증착을 위주로 한 유연 전자 소자들은 무기물질 기반 전자소자 대비 극심한 성능 저하를 보여주었는데, 이를 해결하기 위해 새로운 절연물질을 개발하고 탄소 나노튜브 기반 유연 전자소자에 적용하여 그 가능성을 보여주었다.Chapter 1. Introduction 1 1.1 Discovery of CNTs and their benefits for soft electronic applications 1 1.2 Electrical sorting of CNTs 5 1.3 Deposition methods of solution-processed semiconducting CNTs 7 1.4 Conclusion 23 1.5 References 24 Chapter 2. Stretchable Carbon Nanotube Charge-Trap Floating-Gate Memory and Logic Devices for Wearable Electronics 32 2.1 Introduction 32 2.2 Experimental section 34 2.3 Results and discussion 36 2.4 Conclusion 62 2.5 References 63 Chapter 3. Wearable Electrocardiogram Monitor Using Carbon Nanotube Electronics and Color-Tunable Organic Light-Emitting Diodes 67 3.1 Introduction 67 3.2 Experimental section 70 3.3 Results and discussion 73 3.4 Conclusion 97 3.5 References 98 Chapter 4. Medium-Scale Electronic Skin Based on Carbon Nanotube Transistors with Vacuum-Deposited Stretchable Dielectric Film 102 4.1 Introduction 102 4.2 Experimental section 106 4.3 Result and discussion 111 4.4 Conclusion 135 4.5 References 136Docto

Memristive Non-Volatile Memory Based on Graphene Materials

Resistive random access memory (RRAM), which is considered as one of the most promising next-generation non-volatile memory (NVM) devices and a representative of memristor technologies, demonstrated great potential in acting as an artificial synapse in the industry of neuromorphic systems and artificial intelligence (AI), due its advantages such as fast operation speed, low power consumption, and high device density. Graphene and related materials (GRMs), especially graphene oxide (GO), acting as active materials for RRAM devices, are considered as a promising alternative to other materials including metal oxides and perovskite materials. Herein, an overview of GRM-based RRAM devices is provided, with discussion about the properties of GRMs, main operation mechanisms for resistive switching (RS) behavior, figure of merit (FoM) summary, and prospect extension of GRM-based RRAM devices. With excellent physical and chemical advantages like intrinsic Young’s modulus (1.0 TPa), good tensile strength (130 GPa), excellent carrier mobility (2.0 × 105 cm2∙V−1∙s−1), and high thermal (5000 Wm−1∙K−1) and superior electrical conductivity (1.0 × 106 S∙m−1), GRMs can act as electrodes and resistive switching media in RRAM devices. In addition, the GRM-based interface between electrode and dielectric can have an effect on atomic diffusion limitation in dielectric and surface effect suppression. Immense amounts of concrete research indicate that GRMs might play a significant role in promoting the large-scale commercialization possibility of RRAM devices

연성 및 생재흡수성 전자소자용 비휘발성 메모리 소자와 집적센서 구현

학위논문 (박사)-- 서울대학교 대학원 : 화학생물공학부, 2015. 8. 김대형.Over years, major advances in healthcare have been made through research in the fields of nanomaterials and microelectronics technologies. However, the mechanical and geometrical constraints inherent in the standard forms of rigid electronics have imposed challanges of unique integration and therapeutic delivery in non-invasive and minimally invasive medical devices. Here, we describe two types of multifunctional electronic systems. The first type is wearable-on-the-skin systems that address the challenges via monolithic integration of nanomembranes fabricated by top-down approach, nanotubes and nanoparticles assembled by bottom-up strategies, and stretchable electronics on tissue-like polymeric substrate. The system consists of physiological sensors, non-volatile memory, logic gates, and drug-release actuators. Some quantitative analyses on the operation of each electronics, mechanics, heat-transfer, and drug-diffusion characteristic validated their system-level multi-functionalities. The second type is a bioresorbable electronic stent with drug-infused functionalized nanoparticles that takes flow sensing, temperature monitoring, data storage, wireless power/data transmission, inflammation suppression, localized drug delivery, and photothermal therapy. In vivo and ex vivo animal experiments as well as in vitro cell researches demonstrate its unrecognized potential for bioresorbable electronic implants coupled with bioinert therapeutic nanoparticles in the endovascular system. As demonstrations of these technologies, we herein highlight two representative examples of multifunctional systems in order of increasing degree of invasiveness: electronically enabled wearable patch and endovascular electronic stent that incorporate onboard physiological monitoring, data storage, and therapy under moist and mechanically rigorous conditions.Contents Abstract Chapter 1. Introduction 1.1 Organic flexible and wearable electronics.................................................. 1 1.2 Inorganic flexible and wearable electronics............................................... 14 1.3 Flexible non-volatile memory devices.......................................................... 25 1.4 Bioresorbable materials and devices........................................................... 34 References Chapter 2. Multifunctional wearable devices for diagnosis and therapy of movement disorders 2.1 Introduction ................................................................................. 45 2.2 Experimental Section ......................................................................... 49 2.3 Result and Discussion ........................................................................ 65 2.4 Conclusion ................................................................................... 95 References Chapter 3. Stretchable Carbon Nanotube Charge-Trap Floating-Gate Memory and Logic Devices for Wearable Electronics 3.1 Introduction ................................................................................ 101 3.2 Experimental Section ........................................................................ 104 3.3 Result and Discussion ....................................................................... 107 3.4 Conclusion .................................................................................. 138 References Chapter 4. Bioresorbable Electronic Stent Integrated with Therapeutic Nanoparticles for Endovascular Diseases 4.1 Introduction ................................................................................ 148 4.2 Experimental Section ........................................................................ 151 4.3 Result and Discussion ....................................................................... 173 4.4 Conclusion .................................................................................. 219 References 국문 초록 (Abstract in Korean) .................................................................. 230Docto

Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor

Multi-Functional Optoelectronic Heterostructure Devices Based on Transfer Printing of Nanomaterials

School of Energy and Chemical Engineering (Energy Engineering)Heterostructure devices, combining different electronic properties of semiconductors, offer novel electronic functionalities, which are critically required in emerging applications in high performance and multi-functional electronics. Previously, heterostructure devices have attracted a great attention due to the enhancing performances, adding functionalities and broadening absorption range, through components modulation, resulting in many applications in high electron mobility transistors, non-volatile memory, light emitting diodes, and broadband photodetectors. However, traditional semiconductor heterostructures present significant challenges due to the lattice constant mismatch with other substrates and generation of defects during the direct growth and deposition processes. To address these challenges, a transfer printing was introduced to heterogeneously integrate various nanomaterials onto arbitrary substrates, whereby the bonding at heterointerfaces with a large lattice mismatch is facilitated by van der Waals forces during the transfer printing processes. The transfer printing can provide a freedom of material choice, from zero to three dimensional materials, in the formation of heterostructures without the restriction from lattice mismatch, which enabled various heterostructure devices with unique physical properties. In this thesis, we demonstrate multi-functional optoelectronic heterostructure devices based on transfer printing of nanomaterials. First, in chapter 1, we briefly introduce the research trends in electronic devices and basic concept of transfer printing methods and multi-functional heterostructure devices. In chapter 2, we demonstrate a new type of heterostructure device based on black phosphorus and n-InGaAs nanomembrane semiconductors. The device offers gate-tunable rectification and switching behaviors. In addition, the proposed heterojunction diode can be programed by the modulation of forward current due to the capacitive gating effect. Furthermore, the device is photoresponsive in a spectral range spanning the ultraviolet to near infrared. In chapter 3, we describe the fine patterning technique of silver nanowires on various substrates using vacuum filtration and transfer printing process. This technique provides very simple and cost-effective fabrication for fine patterning of AgNWs electrode for optically transparent and mechanically flexible optoelectronic device applications. This patterning technique can be applied to other nanomaterials such as CNT and graphene and combination of nanomaterials to realize highly flexible and transparent optoelectronic devices. In chapter 4, the large-area MoS2 film and pattering process is demonstrated by shadow mask assisted transfer printing process. The liquid exfoliated MoS2 flakes can be easily patterned by vacuum filtration with polyimide shadow mask. Patterned film is transferred to arbitrary substrate by using transfer printing process for high performance and flexible electronic applications. Therefore, the heterostructure devices made by transfer printing are advantageous in scalability and avoids complicated fabrication process for multi-functional applications.ope

Carrier Transport of Graphene Quantum Device and its Application for Ferroelectric Memory

Department of PhysicsCarrier transport in lateral tunnel junction was studied to apply it for ferroelectric memory devices in theoretical calculations and experimental methods. The edge metal-insulator-metal (EMIM) lateral tunnel junction on ferroelectric layer structure was proven to be a large resistive switching memory device theoretical calculation. The lateral tunnel junction in 2-dimensional material was fabricated with graphene and selectively functionalized graphene. The quantum mechanical tunneling of both 3D and 2D lateral tunnel junction was investigated to apply ferroelectric memory device. Not only the resistive switching memory device, the ferroelectric memory device by using graphene field effect transistor with novel read-out mechanism was studied. Recently, new memory devices substituting currently used DRAM and flash memory are more actively studied because the memory cell size reaches the physical limits less than 10 nanometer scale. Extreme ultraviolet (EUV) photolithography has been adapted to one of the way for overcoming the scaling issue of memory device. Otherwise, the 3D XPoint nonvolatile memory device has been made by Intel Corp. with higher speed than current NAND flash memory. Based on the electrostatic potential change by ferroelectric layer, we studied the new memory device without selection devices by read-out using two crossing lines. Theoretical calculation of tunnel current density at EMIM structure on ferroelectric layer shows the ~1013 switching ratio between polarization up and down state. The read-out mechanism is applying the half of turn on voltage on word and bit line which is connected to the drain and source electrode in lateral tunnel junction. The writing memory cell can be performed with applying voltages on word, bit, and writing line connected to the bottom of ferroelectric layer. This structure is the basic idea for nonvolatile memory device without selection devices. Based on this research, the lateral tunnel junction in two dimensional materials was studied for memory application. We fabricated graphene/fluorinated-graphene/graphene tunnel junction by using selective insulation of graphene layer after E-beam lithography process. Small gap formed in lateral direction between two graphene electrodes works as a tunnel barrier. The theoretical calculation of thermionic emission current and tunneling current were compared with the current-voltage measurement of fabricated tunnel junction. We confirmed that the graphene lateral tunnel junction can be a good candidate for ferroelectric memory devices. Moreover, we studied that read-out of transconductance of graphene field effect transistor on ferroelectric material can be a new way for defining the memory cell state. Using this method, the series resistance of word and bit line cells connected to read-out cell has no effect during read-out. In case of graphene, the transconductance can be switched from negative to positive depending on the polarization direction of ferroelectric layer due to the energy band structure of graphene. We can also apply this read-out mechanism to 3D tunnel junction even though it has no dramatic effect than the graphene field effect transistor. However, considering the commercialization of this kind of memory device, the 3D tunnel junction can be more adaptable than the graphene transistor.clos

Advanced Nanofabrication Technologies for Processing Layered Semiconductors and Device Applications

Two-dimensional layered semiconductor materials, such as transition metal dichalcogenides (TMDCs), recently received a great deal of interest due to their excellent electronic, optoelectronic and mechanical properties, as well as large abundance of relevant bulk materials on earth. Especially for semiconductor-related applications, TMDCs can be used for making highly sensitive sensors, high-performance thin-film transistors (TFTs) that are potentially immune to short-channel effects, and ultra-thin flexible photovoltaic (PV) and photodetection devices. However, to utilize layered semiconductors for innovative device applications, we still need to (i) create scalable manufacturing methods with a high throughput for device production, (ii) develop proper material processing technologies to generate stable and reproducible doping effects in 2D semiconductors, therefore enabling diverse optoelectronic and electronic applications, (iii) advance the device physics to leverage the uniquely advantageous electronic, structural, and mechanical properties of TMDCs in device application fields, such as information processing and data storage. The research presented in this dissertation sought to address the challenges mentioned above with a special focus on the following three topics: (1) development of nanoimprint/nanoprint-based processes for producing device structures based on layered semiconductors; (2) invention of a plasma-assisted doping technology for making TMDC-based nanoelectronic devices such as rectifying diodes and ambipolar transistors; (3) fabrication and characterization of TMDC-based memory devices with multi-bit storage capability, simple device structure, and low production cost. The first part of my thesis presents a nanoimprint/nanoprint-based method for fabricating TMDC-based (e.g., MoS2, WSe2) field-effect transistors. The field effect transistors (FETs) made from produced multilayer MoS2 flakes exhibit very consistent performance with high on/off ratios in the range of 105 -107. The characterization data measured from these FETs show that produced MoS2 flakes have a high uniformity of electronic properties. The second part of my thesis presents a novel plasma-assisted doping technology for modulating the electronic properties of layered semiconductor materials such as TMDCs. Taking MoS2 as an exemplary TMDC under study, via plasma doping, we have demonstrated p-type MoS2 transistors that can be complementary to pristine n-type MoS2 transistors, potentially enabling applications in CMOS circuits. Moreover, via applying plasma doping for selected areas, we have created 2D diodes with high rectification degrees and a superior long-term stability at room temperature. The third part of my thesis presents a study on the abnormal charge-trapping and memory characteristics of few-layer WSe2 transistors. In addition, I present an innovative device application of MoS2 in making floating-gate-free, non-volatile, multi-bit memory FETs, which has a unique combination of excellent retention/endurance characterisitcs, simple device structures and extremely low fabrication cost. These presented works provide nanofabrication and material processing solutions for making nanoelectronic devices based on emerging layered semiconductors, which can be generally utilized for making a broad range of functional devices based on various layered materials (e.g., graphene and topological insulators). Especially, the plasma doping method demonstrated in my research holds the potential to be further developed into an industrial material processing technology for precisely tailoring the band structures of TMDCs to achieve desirable characteristics for various device applications. In addition, the obtained device physics knowledge associated with MoS2 and WSe2-based multi-bit charge memory states is anticipated to greatly leverage the unique electronic and structural properties of layered semiconductors for scalable data storage and emerging analog computing applications.PHDMechanical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/140798/1/mkchen_1.pd