Modeling and analyzing timing faults in transaction level SystemC programs

Since SoC (System on Chip) and NoC (Network on Chip) systems are getting more complex everyday, they are subject to different types of faults including timing faults. Timing has a significant importance in NoC systems. However, their fault-affected models are not studied extensively. In this paper, we present a method for modeling and analyzing timing faults in SystemC Transaction Level Modeling (TLM) programs. The proposed method includes three steps, namely timed model extraction, fault modeling and timed model checking. We use UPPAAL timed automata to formally model the SystemC TLM programs and monitor how the models behave in the presence of timing faults. We analyze our method using a case study. This case study utilizes loosely-timed coding style, which has a loose dependency between timing and data. Copyright 2013 ACM

Modeling and analyzing timing faults in transaction level SystemC programs

In order to increase design productivity of SoC (System on Chip) systems, there is a need to move from implementation-driven design at Register Transfer Language (RTL) to higher levels of abstraction. This move introduces a shift in the development of electronic systems, which has been put into practice as Electronic System Level (ESL) design. The importance of ESL has become reality with Transaction Level Modeling (TLM) standard TLM-2.0 [1]. The C++-based system modeling language SystemC perfectly supports TLM and hence is well-accepted for ESL design in industry