2D-1 Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM

fluctuations of within-die physical process properties are also known as random on-chip variation (OCV). It impacts on the VLSI/SoC design yields significantly. This paper presents a recent silicon test chip experiment result which uses a set of innovative nanometer test structures and Monte-Carlo-based three-dimensional electromagnetic RC simulations to achieve silicon-correlated corner modeling of OCV that can be applied to the upcoming statistics-based timing analysis (SSTA) for design for manufacturability (DFM). Modeling and correlating OCV based on the randomly varying physical process parameters is therefore achieved for the realistic corner modeling of advanced copper and low-K. State-of-the-art sub-90nm VLSI/SoC designs require the BEOL to consist of 6 or more metal layers of copper-alloy interconnects insulated by low-K dielectrics, as shown in Figure 1. Undesired BEOL on-chip variations (OCV) increase with scaled technologies. Therefore, the corresponding interconnect process parameter variations such as metal thickness, metal width, and dielectric thickness must be accurately validated for each metal layer to model the resulting interconnect capacitance and resistance variations. Figure 2 is a typical 3-dimentional (3D) BEOL electromagneticbased capacitance simulation [2] [3] with precise thickness and equivalent rectangular CD of three metal lines above a substrate or a ground plane. I