Mixed-swing Quadrail for Low Power Dual-rail Domino Logic

This paper describes a new mixed-swing topology for dual-rail domino logic that results in a simultaneous energy and delay reduction. HSPICE simulation results for a 1-bit full adder cell show a 24 % delay decrease and a 24 % energy reduction for the mixed-swing topology compared to standard dual-rail domino. Energy and delay trends with supply voltage scaling are also presented for the adder cell. An 8-bit by 8-bit multiplier design with mixedswing dual-rail domino adders is presented. Simulation results show this implementation to be 10 % faster with an 18 % energy savings. 1