300 research outputs found
User microprogrammable processors for high data rate telemetry preprocessing
The use of microprogrammable processors for the preprocessing of high data rate satellite telemetry is investigated. The following topics are discussed along with supporting studies: (1) evaluation of commercial microprogrammable minicomputers for telemetry preprocessing tasks; (2) microinstruction sets for telemetry preprocessing; and (3) the use of multiple minicomputers to achieve high data processing. The simulation of small microprogrammed processors is discussed along with examples of microprogrammed processors
An Imaging Infrared (IIR) seeker using a microprogrammed processor
A recently developed Imaging Infrared Seeker uses a microprogrammed processor to perform gimbal servo control and system interface while performing the seeker functions of automatic target detection, acquisition, and tracking. The automatic detection mode requires up to 80% of the available capability of a high performance microprogrammed processor. Although system complexity was increased significantly, this approach can be cost effective when the basic computation capacity is already available
Hybrid receiver study
The results are presented of a 4 month study to design a hybrid analog/digital receiver for outer planet mission probe communication links. The scope of this study includes functional design of the receiver; comparisons between analog and digital processing; hardware tradeoffs for key components including frequency generators, A/D converters, and digital processors; development and simulation of the processing algorithms for acquisition, tracking, and demodulation; and detailed design of the receiver in order to determine its size, weight, power, reliability, and radiation hardness. In addition, an evaluation was made of the receiver's capabilities to perform accurate measurement of signal strength and frequency for radio science missions
Timing Architecture for ESS
Programa Oficial de Doutoramento en Investigación en Tecnoloxías da Información. 5023V01[Resumo]
O sistema de temporización é unha compoñente fundamental para o control e sincronización de
instalacións industriais e científicas, coma aceleradores de partículas. Nesta tese
traballamos na especificación e desenvolvemento do sistema de temporización para a European
Spallation Source (ESS), a maior fonte de neutróns actualmente en construción. Abordamos
este tra ballo a dous niveis: a especificación do sistema de temporización, e a imple mentación
física de sistemas de control empregando circuítos reconfigurables.
Con respecto á especificación do sistema de temporización, deseñamos e implementamos a
configuración do protocolo de temporización para cumprir cos requirimentos do ESS e ideamos un modo
de operación e unha aplicación para a configuración e control do sistema de temporización.
Tamén presentamos unha ferramenta e unha metodoloxía para imple mentar sistemas de
control empregando FPGAs, coma os nodos do sistema de temporización. ámbalas <lúas están baseadas
en statecharts, unha repre sentación gráfica de sistemas que expande o concepto de máquinas de
estados finitos, orientada a sistemas que necesitan ser reconfigurados rápidamente en múltiples
localizacións minimizando a posibilidade de erros. A ferramenta crea automaticamente código
VHDL sintetizable a partir do statechart do sistema. A metodoloxía explica o procedemento
para implementar o state chart como unha arquitectura microprogramada en FPGAs.[Resumen]
El sistema de temporización es un componente fundamental para el control y sincronización de
instalaciones industriales y científicas, como aceleradores e partículas. En esta tesis
trabajamos en la especificación y desarrollo el sistema de temporización para la European
Spallation Source (ESS), la mayor fuente de neutrones actualmente en construcción.
Abordamos este trabajo en dos niveles: la especificación del sistema de temporización, y la
mplementación física de sistemas de control empleando circuitos reconfig rables.
Con respecto a la especificación del sistema de temporización, diseñamos
e implementamos la configuración del protocolo de temporización para cumplir on los requisitos de
ESS e ideamos un modo de operación y una aplicación ara la configuración y control del sistema
de temporización.
También presentamos una herramienta y una metodología para imple entar sistemas de control
empleando FPGAs, como los nodos del sistema e temporización. Ambas están basadas en statecharts)
una representación gráfica de sistemas que expande el concepto de máquinas de estados
fini os, orientada a sistemas que necesitan ser reconfigurados rápidamente en últiples
localizaciones minimizando la posibilidad de errores. La herramienta crea
automáticamente código VHDL sintetizable a partir del statechart del sistema. La metodología
explica el procedimiento para implementar el statechart como una arquitectura microprogramada en FPGAs.[Abstract]
The timing system is a key component for the control and synchronization of industrial and
scientific facilities, such as particle accelerators. In this thesis we tackle the
specification and development of the timing system for the European Spallation Source (ESS), the
largest neutron source currently in construction. We approach this work at two levels:
the specification of the timing system and the physical implementation of control systems using
reconfigurable hardware.
Regarding the specification of the timing system, we designed and imple mented the configuration
of the timing protocol to fulfil the requirements of ESS and devised an operation mode andan
application for the configuration and control of the timing system.
We also present one too! and one methodology to implement control systems using FPGAs,
such as the nodes of the timing system. Both are based on statecharts, a graphical
representation of systems that expand the concepts of Finite State Machines, targeted at
systems that need to be re configured quickly in multiple locations minimizing the
chance of errors. The too! automatically creates synthesizable VHDL code from a statechart of
the system. The methodology explains the procedure to implement the statechart as a
microprogrammed architecture in FPGAs
Telecommunications Hardware and Software Systems made in CMEA Countries and Yugoslavia
The telecommunications hardware and software systems used in CMEA (Council of Mutual Economic Assistance) countries and Yugoslavia are a most complex field of investigation. For this reason in this study the following approach has been adopted: Rather than collecting and presenting all CMEA telecommunications hardware and software systems in a directory type of form, which would neither be complete nor fully up to date (even at the time of data collection), a general analysis is given, with sufficient detailed information to make it useful. During the analysis we will discuss in depth the different classes of telecommunications hardware and software systems, their past, present, and potential future.
In order to do this, the analysis has to include all major levels of the International Standardization Organization's Open System Interconnection (ISO/OSI) Reference Model--and this is the way we handle the telecommunications hardware and software systems of the CMEA countries and of Yugoslavia
A direct-execution parallel architecture for the Advanced Continuous Simulation Language (ACSL)
A direct-execution parallel architecture for the Advanced Continuous Simulation Language (ACSL) is presented which overcomes the traditional disadvantages of simulations executed on a digital computer. The incorporation of parallel processing allows the mapping of simulations into a digital computer to be done in the same inherently parallel manner as they are currently mapped onto an analog computer. The direct-execution format maximizes the efficiency of the executed code since the need for a high level language compiler is eliminated. Resolution is greatly increased over that which is available with an analog computer without the sacrifice in execution speed normally expected with digitial computer simulations. Although this report covers all aspects of the new architecture, key emphasis is placed on the processing element configuration and the microprogramming of the ACLS constructs. The execution times for all ACLS constructs are computed using a model of a processing element based on the AMD 29000 CPU and the AMD 29027 FPU. The increase in execution speed provided by parallel processing is exemplified by comparing the derived execution times of two ACSL programs with the execution times for the same programs executed on a similar sequential architecture
Multicomputer communication system
A local area network is provided for a plurality of autonomous computers which operate at different rates and under different protocols coupled by network bus adapters to a global bus. A host computer (HC) divides a message file to be transmitted into blocks, each with a header that includes a data type identifier and a trailer. The associated network bus adapter (NBA) then divides the data into packets, each with a header to which a transport header and trailer is added with frame type code which specifies one of three modes of addressing in the transmission of data, namely a physical address mode for computer to computer transmission using two bytes for source and destination addresses, a logical address mode and a data type mode. In the logical address mode, one of the two addressing bytes contains a logical channel number (LCN) established between the transmitting and one or more receiving computers. In the data type mode, one of the addressing bytes contains a code identifying the type of data
Graph model analysis of computer structures
Graph theory is applicable to the solving of problems in nearly every field of scientific study. The purpose of this thesis is to consider its applications in representing and analyzing digital computers. Fundamental graph theory definitions, the types and the properties of the directed graphs, the matrix representation, and several reduction techniques are discussed. The blocking gate method for diagnosing computer systems is described and applied to the Scientific Control Corporation (SCC) 650 for its fault-diagnosis.
Microprogramming has been a significant trend in hardware and software designs of computers. Microprogrammed computers are discussed in comparison to conventional computers. A general scheme utilizing four nodes generates directed graphs for both types of architecture. The directed graphs are studied with respect to the flexibility and cost parameters --Abstract, page ii
Aerospace Applications of Microprocessors
An assessment of the state of microprocessor applications is presented. Current and future requirements and associated technological advances which allow effective exploitation in aerospace applications are discussed
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The distributed computer system
This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University
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