Ultra-thin silicon technology for tactile sensors

In order to meet the requirements of high performance flexible electronics in fast growing portable consumer electronics, robotics and new fields such as Internet of Things (IoT), new techniques such as electronics based on nanostructures, molecular electronics and quantum electronics have emerged recently. The importance given to the silicon chips with thickness below 50 μm is particularly interesting as this will advance the 3D IC technology as well as open new directions for high-performance flexible electronics. This doctoral thesis focusses on the development of silicon–based ultra-thin chip (UTC) for the next generation flexible electronics. UTCs, on one hand can provide processing speed at par with state-of-the-art CMOS technology, and on the other provide the mechanical flexibility to allow smooth integration on flexible substrates. These development form the motivation behind the work presented in this thesis. As the thickness of any silicon piece decreases, the flexural rigidity decreases. The flexural rigidity is defined as the force couple required to bend a non-rigid structure to a unit curvature, and therefore the flexibility increases. The new approach presented in this thesis for achieving thin silicon exploits existing and well-established silicon infrastructure, process, and design modules. The thin chips of thicknesses ranging between 15 μm – 30 μm, were obtained from processed bulk wafer using anisotropic chemical etching. The thesis also presents thin wafer transfer using two-step transfer printing approach, packaging by lamination or encapsulation between two flexible layerand methods to get the electrical connections out of the chip. The devices realised on the wafer as part of front-end processing, consisted capacitors and transistors, have been tested to analyse the effect of bending on the electrical characteristics. The capacitance of metal-oxide-semiconductor (MOS) capacitors increases by ~5% during bending and similar shift is observed in flatband and threshold voltages. Similarly, the carrier mobility in the channel region of metal-oxide-semiconductor field effect transistor (MOSFET) increases by 9% in tensile bending and decreases by ~5% in compressive bending. The analytical model developed to capture the effect of banding on device performance showed close matching with the experimental results. In order to employ these devices as tactile sensors, two types of piezoelectric materials are investigated, and used in extended gate configuration with the MOSFET. Firstly, a nanocomposite of Poly(vinylidene fluoride-co-trifluoroethylene), P(VDF-TrFE) and barium titanate (BT) was developed. The composite, due to opposite piezo and pyroelectric coefficients of constituents, was able to suppress the sensitivity towards temperature when force and temperature varied together, The sensitivity to force in extended gate configuration was measured to be 630 mV/N, and sensitivity to temperature was 6.57 mV/oC, when it was varied during force application. The process optimisation for sputtering piezoelectric Aluminium Nitride (AlN) was also carried out with many parametric variation. AlN does not require poling to exhibit piezoelectricity and therefore offers an attractive alternative for the piezoelectric layer used in devices such as POSFET (where piezoelectric material is directly deposited over the gate area of MOSFET). The optimised process gave highly orientated columnar structure AlN with piezoelectric coefficient of 5.9 pC/N and when connected in extended gate configuration, a sensitivity (normalised change in drain current per unit force) of 2.65 N-1 was obtained

Towards Single-Chip Nano-Systems

Important scientific discoveries are being propelled by the advent of nano-scale sensors that capture weak signals from their environment and pass them to complex instrumentation interface circuits for signal detection and processing. The highlight of this research is to investigate fabrication technologies to integrate such precision equipment with nano-sensors on a single complementary metal oxide semiconductor (CMOS) chip. In this context, several demonstration vehicles are proposed. First, an integration technology suitable for a fully integrated flexible microelectrode array has been proposed. A microelectrode array containing a single temperature sensor has been characterized and the versatility under dry/wet, and relaxed/strained conditions has been verified. On-chip instrumentation amplifier has been utilized to improve the temperature sensitivity of the device. While the flexibility of the array has been confirmed by laminating it on a fixed single cell, future experiments are necessary to confirm application of this device for live cell and tissue measurements. The proposed array can potentially attach itself to the pulsating surface of a single living cell or a network of cells to detect their vital signs

Growth and Oxidation of Graphene and Two-Dimensional Materials for Flexible Electronic Applications

The non-volatile storage of information is becoming increasingly important in our data-driven society. Limitations in conventional devices are driving the research and development of incorporating new materials into conventional device architectures to improve performance, as well as developing an array of emerging memory technologies based on entirely new physical processes. The discovery of graphene allowed for developing new approaches to these problems, both itself and as part of the larger, and ever-expanding family of 2D materials. In this thesis the growth and oxidation of these materials is investigated for implementing into such devices, exploiting some of the unique properties of 2D materials including atomic thinness, mechanical flexibility and tune-ability through chemical modification - to meet some challenges facing the community. This begins with the growth of graphene by chemical vapour deposition for a high quality flexible electrode material, followed by oxidation of graphene for use in resistive memory devices. The theme of oxidation is then extended to another 2D material, HfS2, which is selectively oxidised for use as high-k dielectric in Van der Waals heterostructures for FETs and resistive memory devices. Lastly, a technique for fabrication of graphene-based devices directly on the copper growth substrate is demonstrated for use in flexible devices for sensing touch and humidity

Layer by layer printing of nanomaterials for large-area, flexible electronics

Large-area electronics, including printable and flexible electronics, is an emerging concept which aims to develop electronic components in a cheaper and faster manner, especially on those non-conventional substrates. Being flexible and deformable, this new form of electronics is regarded to hold great promises for various futuristic applications including the internet of things, virtual reality, healthcare monitoring, prosthetics and robotics. However, at present, large-area electronics is still nowhere near the commercialisation stage, which is due to several problems associated with performance, uniformity and reliability, etc. Moreover, although the device’s density is not the major concern in printed electronics, there is still a merit in further increasing the total number of devices in a limited area, in order to achieve more electronic blocks, higher performance and multiple functionalities. In this context, this Ph.D. thesis focuses on the printing of various nanomaterials for the realisation of high-performance, flexible and large-area electronics. Several aspects have been covered in this thesis, including the printing dynamics of quasi-1D NWs, the contact problem in device realisation and the strategy to achieve sequential integration (3D integration) of the as-printed devices, both on rigid and flexible substrates. Promisingly, some of the devices based on the printed nanomaterial show a comparable performance to the state-of-the-art technology. With the demonstrated 3D integration strategy, a highly dense array of electronic devices can be potentially achieved by printing method. This thesis also touches on the problem associated with the circuit and system realisation. Specifically, graphene-based logic gates and NW based UV sensing circuit has been discussed, which shows the promising applications of nanomaterial-based electronics. Future work will be focusing on extending the UV sensing circuit to an active matrix sensor array

Ultra-thin chips for high-performance flexible electronics

Flexible electronics has significantly advanced over the last few years, as devices and circuits from nanoscale structures to printed thin films have started to appear. Simultaneously, the demand for high-performance electronics has also increased because flexible and compact integrated circuits are needed to obtain fully flexible electronic systems. It is challenging to obtain flexible and compact integrated circuits as the silicon based CMOS electronics, which is currently the industry standard for high-performance, is planar and the brittle nature of silicon makes bendability difficult. For this reason, the ultra-thin chips from silicon is gaining interest. This review provides an in-depth analysis of various approaches for obtaining ultra-thin chips from rigid silicon wafer. The comprehensive study presented here includes analysis of ultra-thin chips properties such as the electrical, thermal, optical and mechanical properties, stress modelling, and packaging techniques. The underpinning advances in areas such as sensing, computing, data storage, and energy have been discussed along with several emerging applications (e.g., wearable systems, m-Health, smart cities and Internet of Things etc.) they will enable. This paper is targeted to the readers working in the field of integrated circuits on thin and bendable silicon; but it can be of broad interest to everyone working in the field of flexible electronics

Thermo-Mechanical Effects Of Thermal Cycled Copper Through Silicon Vias

The semiconductor industry is currently facing transistor scaling issues due to fabrication thresholds and quantum effects. In this \u27More-Than-Moore\u27 era, the industry is developing new ways to increase device performance, such as stacking chips for three-dimensional integrated circuits (3D-IC). The 3D-IC\u27s superior performance over their 2D counterparts can be attributed to the use of vertical interconnects, or through silicon vias (TSV). These interconnects are much shorter, reducing signal delay. However TSVs are susceptible to various thermo-mechanical reliability concerns. Heating during fabrication and use, in conjunction with coefficient of thermal expansion mismatch between the copper TSVs and silicon substrate, create harmful stresses in the system. The purpose of this work is to evaluate the signal integrity of Cu-TSVs and determine the major contributing factors of the signal degradation upon in-use conditions. Two series of samples containing blind Cu-TSVs embedded in a Si substrate were studied, each having different types and amounts of voids from manufacturing. The samples were thermally cycled up to 2000 times using three maximum temperatures to simulate three unique in-use conditions. S11 parameter measurements were then conducted to determine the signal integrity of the TSVs. To investigate the internal response from cycling, a protocol was developed for cross-sectioning the copper TSVs. Voids were measured using scanning electron microscope and focused ion beam imaging of the cross-sections, while the microstructural evolution of the copper was monitored with electron backscattering diffraction. An increase in void area was found to occur after cycling. This is thought to be the major contributing factor in the signal degradation of the TSVs, since no microstructural changes were observed in the copper

Active Metal-Insulator-Metal Plasmonic Devices

As the field of photonics constantly strives for ever smaller devices, the diffraction limit of light emerges as a fundamental limitation in this pursuit. A growing number of applications for optical "systems on a chip" have inspired new ways of circumventing this issue. One such solution to this problem is active plasmonics. Active plasmonics is an emerging field that enables light compression into nano-structures based on plasmon resonances at a metal-dielectric interface and active modulation of these plasmons with an applied external field. One area of active plasmonics has focused on replacing the dielectric layer in these waveguides with an electro-optic material and designing the resulting structures in such a way that the transmitted light can be modulated. These structures can be utilized to design a wide range of devices including optical logic gates, modulators, and filters. This thesis focuses on replacing the dielectric layer within a metal-insulator-metal plasmonic waveguide with a range of electrically active materials. By applying an electric field between the metal layers, we take advantage of the electro-optic effect in lithium niobate, and modulating the carrier density distribution across the structure in n-type silicon and indium tin oxide. The first part of this thesis looks at fabricating metal-insulator-metal waveguides with ion-implantation induced layer transferred lithium niobate. The process is analyzed from a thermodynamic standpoint and the ion-implantation conditions required for layer transfer are determined. The possible failure mechanisms that can occur during this process are analyzed from a thin-film mechanics standpoint, and a metal-bonding method to improve successful layer transfer is proposed and analyzed. Finally, these devices are shown to naturally filter white light into individual colors based on the interference of the different optical modes within the dielectric layer. Full-field electromagnetic simulations show that these devices can preferentially couple to any of the primary colors and can tune the output color of the device with an applied field. The second part of this thesis looks at fabricating metal-insulator-metal waveguides with n-type silicon and indium tin oxide. With the silicon device, by tuning the thicknesses of the layers used in a metal-oxide semiconductor geometry, the device we call the "plasMOStor" can support plasmonic modes as well as exactly one photonic mode. With an applied field, this photonic mode is pushed into cutoff and modulation depths of 11.2 dB are achieved. With the indium tin oxide device, the doping density within the material is changed and as a result, the plasma frequency is shifted into the near-infrared and visible wavelengths. Using spectroscopic ellipsometry, the structure is characterized with and without an applied electric field, and measurements show that when an accumulation layer is formed within the structure, the index of refraction within that layer is significantly changed and as a result, will change the optical modes supported in such a structure.</p