2 research outputs found
Metastability-Resilient Synchronization FIFO for SFQ Logic
Digital single-flux quantum (SFQ) technology promises to meet the demands of
ultra low power and high speed computing needed for future exascale
supercomputing systems. The combination of ultra high clock frequencies,
gate-level pipelines, and numerous sources of variability in SFQ circuits,
however, make low-skew global clock distribution a challenge. This motivates
the support of multiple independent clock domains and related clock domain
crossing circuits that enable reliable communication across domains. Existing
J-SIM simulation models indicate that setup violations can cause clock-to-Q
increases of up to 100%. This paper first shows that naive SFQ clock domain
crossing (CDC) first-in-first-out buffers (FIFOs) are vulnerable to these delay
increases, motivating the need for more robust CDC FIFOs. Inspired by CMOS
multi-flip-flop asynchronous FIFO synchronizers, we then propose a novel 1-bit
metastability-resilient SFQ CDC FIFO that simulations show delivers over a 1000
reduction in logical error rate at 30 GHz. Moreover, for a 10-stage FIFO, the
Josephson junction (JJ) area of our proposed design is only 7.5% larger than
the non-resilient counterpart. Finally, we propose design guidelines that
define the minimal FIFO depth subject to both throughput and burstiness
constraints.Comment: Accepted in ISEC 201
Modeling and Characterization of Metastability in Single Flux Quantum (SFQ) Synchronizers
Despite the promises of low-power and high-frequency of single-flux quantum
(SFQ) technology, scaling these circuits remains a serious challenge that
motivates the support of multiple SFQ clock domains. Towards this end, this
paper analyzes the impact of setup time violations and metastability in SFQ
circuits comparing the derived analytical models to their CMOS counterparts. It
then extends this model to estimate the Mean Time Between Failure (MTBF) of
flip-flop-based synchronizers and curve fits this model to simulations in the
state-of-the-art SFQ5ee process. Interestingly, we find a two-flop SFQ
synchronizer has an estimated MTBF of 10^6 years