Neuro-Fuzzy Computing System with the Capacity of Implementation on Memristor-Crossbar and Optimization-Free Hardware Training

In this paper, first we present a new explanation for the relation between logical circuits and artificial neural networks, logical circuits and fuzzy logic, and artificial neural networks and fuzzy inference systems. Then, based on these results, we propose a new neuro-fuzzy computing system which can effectively be implemented on the memristor-crossbar structure. One important feature of the proposed system is that its hardware can directly be trained using the Hebbian learning rule and without the need to any optimization. The system also has a very good capability to deal with huge number of input-out training data without facing problems like overtraining.Comment: 16 pages, 11 images, submitted to IEEE Trans. on Fuzzy system

Spiking ink drop spread clustering algorithm and its memristor crossbar conceptual hardware design

In this study, a novel neuro-fuzzy clustering algorithm is proposed based on spiking neural network and ink drop spread (IDS) concepts. The proposed structure is a one-layer artificial neural network with leaky integrate and fire (LIF) neurons. The structure implements the IDS algorithm as a fuzzy concept. Each training data will result in firing the corresponding input neuron and its neighboring neurons. A synchronous time coding algorithm is used to manage input and output neurons firing time. For an input data, one or several output neurons of the network will fire; confidence degree of the network to outputs is defined as the relative delay of the firing times with respect to the synchronous pulse. A memristor crossbar-based hardware is utilized for hardware implementation of the proposed algorithm. The simulation result corroborates that the proposed algorithm can be used as a neuro-fuzzy clustering and vector quantization algorithm

Modeling and design of memristor-based fuzzy systems

The incessant down scaling of CMOS technology has been the main driving force for the semiconductor industry over the past decades. Yet, as process variations and leakage current continue to exhibit more pronounced effect with every technology node, this down scaling paradigm is expected to saturate in the few coming years. This prospect has led the research community to seek new technologies to surpass those challenges. Amongst the promising candidates is the memristor technology recently characterized by HP Labs. The miniaturized features and the peculiar behavior exhibited by the memsitor make it very well suited in some applications. For instance, memrsitors are used as memory cells in state-of-the-art memories known as Resistive RAMs in which the non-volatility of the memristor is exploited. The programmable nature of the memristor has made it a powerful candidate in neuromorphic and fuzzy systems that, in essence, go beyond the classical Von Neumann computing paradigm. In such systems, ideas from Artificial Intelligence, that for so long have been implemented on the software level, are implemented as electronic circuitry which renders benefits such as compact area and reduced power consumption. This work focuses on memrsitor-based Fuzzy applications. First, memristor-based Min-Max circuit used in the Fuzzy Inference engine is analyzed. It is proven that memrsitor-based Min-Max circuits can be extended to an arbitrary number of inputs ‘N’ under the proper design constraints. In addition, the effect of the memristor threshold is analyzed and a closed form expression is derived. It is shown that, for a given memristor with a specific OFF resistance and threshold current, there is a trade-off between the size and the resolution of the circuit. Then, a memrsitor-based Defuzzifier circuit is proposed. A major challenge in Defuzzifiers is their area occupancy due to the use of Multiplier and Divider circuits. In this design, the memrsitor analog programmability is leveraged to reduce the multiplication operation into simple Ohm’s Law which alleviates the need for dedicated hardware for multiplier circuit and, accordingly, reduces the area occupancy