A low-complexity turbo decoder architecture for energy-efficient wireless sensor networks

Turbo codes have recently been considered for energy-constrained wireless communication applications, since they facilitate a low transmission energy consumption. However, in order to reduce the overall energy consumption, Look-Up- Table-Log-BCJR (LUT-Log-BCJR) architectures having a low processing energy consumption are required. In this paper, we decompose the LUT-Log-BCJR architecture into its most fundamental Add Compare Select (ACS) operations and perform them using a novel low-complexity ACS unit. We demonstrate that our architecture employs an order of magnitude fewer gates than the most recent LUT-Log-BCJR architectures, facilitating a 71% energy consumption reduction. Compared to state-of- the-art Maximum Logarithmic Bahl-Cocke-Jelinek-Raviv (Max- Log-BCJR) implementations, our approach facilitates a 10% reduction in the overall energy consumption at ranges above 58 m

Mapping the SISO module of the Turbo decoder to a FPFA

In the CHAMELEON project a reconfigurable systems-architecture, the Field Programmable Function Array (FPFA) is introduced. FPFAs are reminiscent to FPGAs, but have a matrix of ALUs and lookup tables instead of Configurable Logic Blocks (CLBs). The FPFA can be regarded as a low power reconfigurable accelerator for an application specific domain. In this paper we show how the SISO (Soft Input Soft Output) module of the Turbo decoding algorithm can be mapped on the reconfigurable FPFA

Turbo Decoding and Detection for Wireless Applications

A historical perspective of turbo coding and turbo transceivers inspired by the generic turbo principles is provided, as it evolved from Shannon’s visionary predictions. More specifically, we commence by discussing the turbo principles, which have been shown to be capable of performing close to Shannon’s capacity limit. We continue by reviewing the classic maximum a posteriori probability decoder. These discussions are followed by studying the effect of a range of system parameters in a systematic fashion, in order to gauge their performance ramifications. In the second part of this treatise, we focus our attention on the family of iterative receivers designed for wireless communication systems, which were partly inspired by the invention of turbo codes. More specifically, the family of iteratively detected joint coding and modulation schemes, turbo equalization, concatenated spacetime and channel coding arrangements, as well as multi-user detection and three-stage multimedia systems are highlighted

Self-concatenated code design and its application in power-efficient cooperative communications

In this tutorial, we have focused on the design of binary self-concatenated coding schemes with the help of EXtrinsic Information Transfer (EXIT) charts and Union bound analysis. The design methodology of future iteratively decoded self-concatenated aided cooperative communication schemes is presented. In doing so, we will identify the most important milestones in the area of channel coding, concatenated coding schemes and cooperative communication systems till date and suggest future research directions

Design and optimization of joint iterative detection and decoding receiver for uplink polar coded SCMA system

SCMA and polar coding are possible candidates for 5G systems. In this paper, we firstly propose the joint iterative detection and decoding (JIDD) receiver for the uplink polar coded sparse code multiple access (PC-SCMA) system. Then, the EXIT chart is used to investigate the performance of the JIDD receiver. Additionally, we optimize the system design and polar code construction based on the EXIT chart analysis. The proposed receiver integrates the factor graph of SCMA detector and polar soft-output decoder into a joint factor graph, which enables the exchange of messages between SCMA detector and polar decoder iteratively. Simulation results demonstrate that the JIDD receiver has better BER performance and lower complexity than the separate scheme. Specifically, when polar code length N=256 and code rate R=1/2 , JIDD outperforms the separate scheme 4.8 and 6 dB over AWGN channel and Rayleigh fading channel, respectively. It also shows that, under 150% system loading, the JIDD receiver only has 0.3 dB performance loss compared to the single user uplink PC-SCMA over AWGN channel and 0.6 dB performance loss over Rayleigh fading channel