Managing Memory Access Latency in Packet Processing Systems

Abstract: In this study, we refute the popular belief [1, 2] that packet processing does not benefit from data-caching. We show that a small data-cache of 8KB can bring down the packet processing time by much as 50-90%, while reducing the off-chip memory bandwidth usage by about 60-95%. We also show that, unlike general-purpose computing, packet processing, due to its memoryintensive nature, cannot rely exclusively on data-caching to eliminate the memory bottleneck completely