Low Power Dissipation in Johnson Counter using DFAL Technique

This paper presents a new method for minimizing power dissipation in 4-bit Johnson counter in which Diode-Free adiabatic Logic(DFAL) is used.Power dissipation of the diodes is eliminated by removing diodes from charging and discharging path.Performance of the proposed logic is analyzed and compared with that of CMOS based circuits. All the simulation are carried out in VIRTUOSO spectre simulator of CADENCE 90nm technology .The paper provides low power dissipation using DFAL logic,which has shown better improvement than conventional CMOS design

Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic

Efficiency of adiabatic logic circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. The lesser will be these losses circuit will be more energy efficient. In this paper, a new approach is presented for minimizing power consumption in quasistatic energy recovery logic (QSERL) circuit which involves optimization by removing the nonadiabatic losses completely by replacing the diodes with MOSFETs whose gates are controlled by power clocks. Proposed circuit inherits the advantages of quasistatic ERL (QSERL) family but is with improved power efficiency and driving ability. In order to demonstrate workability of the newly developed circuit, a 4 × 4 bit array multiplier circuit has been designed. A mathematical expression to calculate energy dissipation in proposed inverter is developed. Performance of the proposed logic (improved quasistatic energy recovery logic (IQSERL)) is analyzed and compared with CMOS and reported QSERL in their representative inverters and multipliers in VIRTUOSO SPECTRE simulator of Cadence in 0.18 μm UMC technology. In our proposed (IQSERL) inverter the power efficiency has been improved to almost 20% up to 50 MHz and 300 fF external load capacitance in comparison to CMOS and QSERL circuits