Design and VLSI implementation of a decimation filter for hearing Aid applications

Approximately 10% of the world’s population suffers from some type of hearing loss, yet only small percentage of this statistic use the hearing aid. The stigma associated with wearing a hearing aid, customer dissatisfaction with hearing aid performance, the cost and the battery life. Through the use of digital signal processing the digital hearing aid now offers what the analog hearing aid cannot offer. Currently lot of attention is being given to low power VLSI design. More and more people around the world suffer from hearing losses. The increasing average age and the growing population are the main reasons for this. The decimation filter used for hearing aid applications is designed and implemented both in MATLAB and VHDL. The decimation filter is designed using the distributed arithmetic multiplier in VHDL. Each digital filter structure is simulated using Matlab and its complete architecture is captured using Simulink. The resulting architecture is hardware efficient and consumes less power compared to conventional decimation filters. Compared to the comb-FIR-FIR architecture, the designed decimation filter architecture using Comb-half band FIR-FIR contributes to a hardware saving and reduces the power dissipation

Partially reconfigurable TVWS transceiver for use in UK and US markets

With more and more countries opening up sections of unlicensed spectrum for use by TV White Space (TVWS) devices, the prospect of building a device capable of operating in more than one world region is appealing. The difficulty is that the locations of TVWS bands within the radio spectrum are not globally harmonised. With this problem in mind, the purpose of this paper is to present a TVWS transceiver design which is capable of being reconfigured to operate in both the UK and US spectrum. We present three different configurations: one covering the UK TVWS spectrum and the remaining two covering the various locations of the US TVWS bands

A Reconfigurable Tile-Based Architecture to Compute FFT and FIR Functions in the Context of Software-Defined Radio

Software-defined radio (SDR) is the term used for flexible radio systems that can deal with multiple standards. For an efficient implementation, such systems require appropriate reconfigurable architectures. This paper targets the efficient implementation of the most computationally intensive kernels of two significantly different standards, viz. Bluetooth and HiperLAN/2, on the same reconfigurable hardware. These kernels are FIR filtering and FFT. The designed architecture is based on a two-dimensional arrangement of 17 tiles. Each tile contains a multiplier, an adder, local memory and multiplexers allowing flexible communication with the neighboring tiles. The tile-base data path is complemented with a global controller and various memories. The design has been implemented in SystemC and simulated extensively to prove equivalence with a reference all-software design. It has also been synthesized and turns out to outperform significantly other reconfigurable designs with respect to speed and area

Efficient TV white space filter bank transceiver

Future devices operating in the TV white space (TVWS) spectrum will require to access different bands at different locations and times in order to avoid interference to incumbent users, requiring agility and sufficient spectral masks to satisfy regulators. Further, with very high-speed ADCs and DACs becoming reality, the purpose of this paper is to present a transceiver front-end capable of simultaneously up- and downconverting a significant portion of the UHF band. The proposed approach takes a two-stage filter-bank conversion for implementation on state-of-the-art FPGAs. We present three different parameterisations, which are compatible with the 40 TVWS channels between 470 and 790MHz in Europe, and compare them in terms of complexity and latency

VLSI Implementation of Cascaded Integrator Comb Filters for DSP Applications

The recursive comb filters or Cascaded Integrator Comb filter (CIC) are commonly used as decimators for the sigma delta modulators. This paper presents the VLSI implementation, analysis and design of high speed CIC filters which are based on a low-pass filter. These filters are used in the signal decimation which has the effect on reducing the sampling rate. It is also chosen because its attractive property of both low power and low complexity since it dose not required a multiplier. Simulink toolbox available in Matlab software which is used to simulator and Verilog HDL coding help to verify the functionality of the CIC filters. Design procedures and examples are given for CIC filter with emphasis on frequency response, transfer function and register width. The implementation results show using Modified Carry Look-ahead Adder for summation and also apply pipelined filter structure enhanced high speed and make it more compatible for DSP applications

A New Low Complexity Uniform Filter Bank Based on the Improved Coefficient Decimation Method

In this paper, we propose a new uniform filter bank (FB) based on the improved coefficient decimation method (ICDM). In the proposed FB’s design, the ICDM is used to obtain different multi-band frequency responses using a single lowpass prototype filter. The desired subbands are individually obtained from these multi-band frequency responses by using low order frequency response masking filters and their corresponding ICDM output frequency responses. We show that the proposed FB is a very low complexity alternative to the other FBs in literature, especially the widely used discrete Fourier transform based FB (DFTFB) and the CDM based FB (CDFB). The proposed FB can have a higher number of subbands with twice the center frequency resolution when compared with the CDFB and DFTFB. Design example and implementation results show that our FB achieves 86.59% and 58.84% reductions in resource utilizations and 76.95% and 47.09% reductions in power consumptions when compared with the DFTFB and CDFB respectively