Low Power VLSI Sequential Circuit Architecture Using Critical Race Control ±

This paper describes a new architecture for VLSI sequential circuits and a method to control the critical races that appears subsequently in their feedback loops. This architecture reduces the number of gates resulting in lower power consumption and smaller area of implementation without incurring significant speed penalty. The critical races are controlled by introducing a delay difference between the sections of the loop. This is implemented by scaling the transmission gates already present in the circuit. This method which sizes transistors in close proximity is insensitive to variations in internal and external operating conditions. The paper presents low-power implementation of conventional circuits and of new circuits providing a higher level of integration. When used with asynchronous circuits this architecture enables the operation of circuits that are unusable using present techniques