60,963 research outputs found
Toward bio-inspired information processing with networks of nano-scale switching elements
Unconventional computing explores multi-scale platforms connecting
molecular-scale devices into networks for the development of scalable
neuromorphic architectures, often based on new materials and components with
new functionalities. We review some work investigating the functionalities of
locally connected networks of different types of switching elements as
computational substrates. In particular, we discuss reservoir computing with
networks of nonlinear nanoscale components. In usual neuromorphic paradigms,
the network synaptic weights are adjusted as a result of a training/learning
process. In reservoir computing, the non-linear network acts as a dynamical
system mixing and spreading the input signals over a large state space, and
only a readout layer is trained. We illustrate the most important concepts with
a few examples, featuring memristor networks with time-dependent and history
dependent resistances
The prospects for mathematical logic in the twenty-first century
The four authors present their speculations about the future developments of
mathematical logic in the twenty-first century. The areas of recursion theory,
proof theory and logic for computer science, model theory, and set theory are
discussed independently.Comment: Association for Symbolic Logi
Implementation of the conjugate gradient algorithm on FPGA devices
Results of porting parts of the Lattice Quantum Chromodynamics code to modern
FPGA devices are presented. A single-node, double precision implementation of
the Conjugate Gradient algorithm is used to invert numerically the Dirac-Wilson
operator on a 4-dimensional grid on a Xilinx Zynq evaluation board. The code is
divided into two software/hardware parts in such a way that the entire
multiplication by the Dirac operator is performed in programmable logic, and
the rest of the algorithm runs on the ARM cores. Optimized data blocks are used
to efficiently use data movement infrastructure allowing to reach intervals of
1 clock cycle. We show that the FPGA implementation can offer a comparable
performance compared to that obtained using Intel Xeon Phi KNL.Comment: Proceedings of the 36th Annual International Symposium on Lattice
Field Theory - LATTICE201
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