175 research outputs found
Bridging the Gap Between Layout Pattern Sampling and Hotspot Detection via Batch Active Learning
Layout hotpot detection is one of the main steps in modern VLSI design. A
typical hotspot detection flow is extremely time consuming due to the
computationally expensive mask optimization and lithographic simulation. Recent
researches try to facilitate the procedure with a reduced flow including
feature extraction, training set generation and hotspot detection, where
feature extraction methods and hotspot detection engines are deeply studied.
However, the performance of hotspot detectors relies highly on the quality of
reference layout libraries which are costly to obtain and usually predetermined
or randomly sampled in previous works. In this paper, we propose an active
learning-based layout pattern sampling and hotspot detection flow, which
simultaneously optimizes the machine learning model and the training set that
aims to achieve similar or better hotspot detection performance with much
smaller number of training instances. Experimental results show that our
proposed method can significantly reduce lithography simulation overhead while
attaining satisfactory detection accuracy on designs under both DUV and EUV
lithography technologies.Comment: 8 pages, 7 figure
Automatic Layout Generation with Applications in Machine Learning Engine Evaluation
Machine learning-based lithography hotspot detection has been deeply studied
recently, from varies feature extraction techniques to efficient learning
models. It has been observed that such machine learning-based frameworks are
providing satisfactory metal layer hotspot prediction results on known public
metal layer benchmarks. In this work, we seek to evaluate how these machine
learning-based hotspot detectors generalize to complicated patterns. We first
introduce a automatic layout generation tool that can synthesize varies layout
patterns given a set of design rules. The tool currently supports both metal
layer and via layer generation. As a case study, we conduct hotspot detection
on the generated via layer layouts with representative machine learning-based
hotspot detectors, which shows that continuous study on model robustness and
generality is necessary to prototype and integrate the learning engines in DFM
flows. The source code of the layout generation tool will be available at
https://github. com/phdyang007/layout-generation.Comment: 6 pages, submitted to 1st ACM/IEEE Workshop on Machine Learning for
CAD (MLCAD) for revie
VLSI Mask Optimization: From Shallow To Deep Learning
VLSI mask optimization is one of the most critical stages in
manufacturability aware design, which is costly due to the complicated mask
optimization and lithography simulation. Recent researches have shown prominent
advantages of machine learning techniques dealing with complicated and big data
problems, which bring potential of dedicated machine learning solution for DFM
problems and facilitate the VLSI design cycle. In this paper, we focus on a
heterogeneous OPC framework that assists mask layout optimization. Preliminary
results show the efficiency and effectiveness of proposed frameworks that have
the potential to be alternatives to existing EDA solutions.Comment: 6 pages; accepted by 25th Asia and South Pacific Design Automation
Conference (ASP-DAC 2020
On Improving Hotspot Detection Through Synthetic Pattern-Based Database Enhancement
Continuous technology scaling and the introduction of advanced technology
nodes in Integrated Circuit (IC) fabrication is constantly exposing new
manufacturability issues. One such issue, stemming from complex interaction
between design and process, is the problem of design hotspots. Such hotspots
are known to vary from design to design and, ideally, should be predicted early
and corrected in the design stage itself, as opposed to relying on the foundry
to develop process fixes for every hotspot, which would be intractable. In the
past, various efforts have been made to address this issue by using a known
database of hotspots as the source of information. The majority of these
efforts use either Machine Learning (ML) or Pattern Matching (PM) techniques to
identify and predict hotspots in new incoming designs. However, almost all of
them suffer from high false-alarm rates, mainly because they are oblivious to
the root causes of hotspots. In this work, we seek to address this limitation
by using a novel database enhancement approach through synthetic pattern
generation based on carefully crafted Design of Experiments (DOEs).
Effectiveness of the proposed method against the state-of-the-art is evaluated
on a 45nm process using industry-standard tools and designs
Data Efficient Lithography Modeling with Transfer Learning and Active Data Selection
Lithography simulation is one of the key steps in physical verification,
enabled by the substantial optical and resist models. A resist model bridges
the aerial image simulation to printed patterns. While the effectiveness of
learning-based solutions for resist modeling has been demonstrated, they are
considerably data-demanding. Meanwhile, a set of manufactured data for a
specific lithography configuration is only valid for the training of one single
model, indicating low data efficiency. Due to the complexity of the
manufacturing process, obtaining enough data for acceptable accuracy becomes
very expensive in terms of both time and cost, especially during the evolution
of technology generations when the design space is intensively explored. In
this work, we propose a new resist modeling framework for contact layers,
utilizing existing data from old technology nodes and active selection of data
in a target technology node, to reduce the amount of data required from the
target lithography configuration. Our framework based on transfer learning and
active learning techniques is effective within a competitive range of accuracy,
i.e., 3-10X reduction on the amount of training data with comparable accuracy
to the state-of-the-art learning approach
An Automated System for Checking Lithography Friendliness of Standard Cells
At advanced process nodes, lithography weakpoints can exist in physical
layouts of integrated circuit designs even if the layouts pass design rule
checking (DRC). Existence of lithography weakpoints in a physical layout can
cause manufacturability issues, which in turn can result in yield losses. In
our experiments, we have found that specific standard cells have tendencies to
create lithography weakpoints after their cell instances are placed and routed,
even though each of these cells does not contain any lithography weakpoint
before performing placement and routing. In addition, our experiments have
shown that abutted standard cell instances can induce lithography weakpoints.
Therefore, in this paper, we propose methodologies that are used in a novel
software system for checking standard cells in terms of the aforementioned
lithography issues. Specifically, the software system is capable of detecting
and sorting problematic standard cells which are prone to generate lithography
weakpoints, as well as reporting standard cells that should not be abutted.
Methodologies proposed in this paper allow us to reduce or even prevent the
generation of undesirable lithography weakpoints during the physical synthesis
phase of designing a digital integrated circuit
Painting on Placement: Forecasting Routing Congestion using Conditional Generative Adversarial Nets
Physical design process commonly consumes hours to days for large designs,
and routing is known as the most critical step. Demands for accurate routing
quality prediction raise to a new level to accelerate hardware innovation with
advanced technology nodes. This work presents an approach that forecasts the
density of all routing channels over the entire floorplan, with features
collected up to placement, using conditional GANs. Specifically, forecasting
the routing congestion is constructed as an image translation (colorization)
problem. The proposed approach is applied to a) placement exploration for
minimum congestion, b) constrained placement exploration and c) forecasting
congestion in real-time during incremental placement, using eight designs
targeting a fixed FPGA architecture.Comment: 6 pages, 9 figures, to appear at DAC'1
Are Adversarial Perturbations a Showstopper for ML-Based CAD? A Case Study on CNN-Based Lithographic Hotspot Detection
There is substantial interest in the use of machine learning (ML) based
techniques throughout the electronic computer-aided design (CAD) flow,
particularly those based on deep learning. However, while deep learning methods
have surpassed state-of-the-art performance in several applications, they have
exhibited intrinsic susceptibility to adversarial perturbations --- small but
deliberate alterations to the input of a neural network, precipitating
incorrect predictions. In this paper, we seek to investigate whether
adversarial perturbations pose risks to ML-based CAD tools, and if so, how
these risks can be mitigated. To this end, we use a motivating case study of
lithographic hotspot detection, for which convolutional neural networks (CNN)
have shown great promise. In this context, we show the first adversarial
perturbation attacks on state-of-the-art CNN-based hotspot detectors;
specifically, we show that small (on average 0.5% modified area), functionality
preserving and design-constraint satisfying changes to a layout can nonetheless
trick a CNN-based hotspot detector into predicting the modified layout as
hotspot free (with up to 99.7% success). We propose an adversarial retraining
strategy to improve the robustness of CNN-based hotspot detection and show that
this strategy significantly improves robustness (by a factor of ~3) against
adversarial attacks without compromising classification accuracy
Machine Learning for Electronic Design Automation: A Survey
With the down-scaling of CMOS technology, the design complexity of very
large-scale integrated (VLSI) is increasing. Although the application of
machine learning (ML) techniques in electronic design automation (EDA) can
trace its history back to the 90s, the recent breakthrough of ML and the
increasing complexity of EDA tasks have aroused more interests in incorporating
ML to solve EDA tasks. In this paper, we present a comprehensive review of
existing ML for EDA studies, organized following the EDA hierarchy.Comment: Accepted by TODAES. The first 10 authors are ordered alphabeticall
Bias Busters: Robustifying DL-based Lithographic Hotspot Detectors Against Backdooring Attacks
Deep learning (DL) offers potential improvements throughout the CAD
tool-flow, one promising application being lithographic hotspot detection.
However, DL techniques have been shown to be especially vulnerable to inference
and training time adversarial attacks. Recent work has demonstrated that a
small fraction of malicious physical designers can stealthily "backdoor" a
DL-based hotspot detector during its training phase such that it accurately
classifies regular layout clips but predicts hotspots containing a specially
crafted trigger shape as non-hotspots. We propose a novel training data
augmentation strategy as a powerful defense against such backdooring attacks.
The defense works by eliminating the intentional biases introduced in the
training data but does not require knowledge of which training samples are
poisoned or the nature of the backdoor trigger. Our results show that the
defense can drastically reduce the attack success rate from 84% to ~0%
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