4,657 research outputs found
Layout Decomposition for Quadruple Patterning Lithography and Beyond
For next-generation technology nodes, multiple patterning lithography (MPL)
has emerged as a key solution, e.g., triple patterning lithography (TPL) for
14/11nm, and quadruple patterning lithography (QPL) for sub-10nm. In this
paper, we propose a generic and robust layout decomposition framework for QPL,
which can be further extended to handle any general K-patterning lithography
(K4). Our framework is based on the semidefinite programming (SDP)
formulation with novel coloring encoding. Meanwhile, we propose fast yet
effective coloring assignment and achieve significant speedup. To our best
knowledge, this is the first work on the general multiple patterning
lithography layout decomposition.Comment: DAC'201
Scalable Multiple Patterning Layout Decomposition Implemented by a Distribution Evolutionary Algorithm
As the feature size of semiconductor technology shrinks to 10 nm and beyond,
the multiple patterning lithography (MPL) attracts more attention from the
industry. In this paper, we model the layout decomposition of MPL as a
generalized graph coloring problem, which is addressed by a distribution
evolutionary algorithm based on a population of probabilistic model (DEA-PPM).
DEA-PPM can strike a balance between decomposition results and running time,
being scalable for varied settings of mask number and lithography resolution.
Due to its robustness of decomposition results, this could be an alternative
technique for multiple patterning layout decomposition in next-generation
technology nodes
A High-Performance Triple Patterning Layout Decomposer with Balanced Density
Triple patterning lithography (TPL) has received more and more attentions
from industry as one of the leading candidate for 14nm/11nm nodes. In this
paper, we propose a high performance layout decomposer for TPL. Density
balancing is seamlessly integrated into all key steps in our TPL layout
decomposition, including density-balanced semi-definite programming (SDP),
density-based mapping, and density-balanced graph simplification. Our new TPL
decomposer can obtain high performance even compared to previous
state-of-the-art layout decomposers which are not balanced-density aware, e.g.,
by Yu et al. (ICCAD'11), Fang et al. (DAC'12), and Kuang et al. (DAC'13).
Furthermore, the balanced-density version of our decomposer can provide more
balanced density which leads to less edge placement error (EPE), while the
conflict and stitch numbers are still very comparable to our
non-balanced-density baseline
Methodology for standard cell compliance and detailed placement for triple patterning lithography
As the feature size of semiconductor process further scales to sub-16nm
technology node, triple patterning lithography (TPL) has been regarded one of
the most promising lithography candidates. M1 and contact layers, which are
usually deployed within standard cells, are most critical and complex parts for
modern digital designs. Traditional design flow that ignores TPL in early
stages may limit the potential to resolve all the TPL conflicts. In this paper,
we propose a coherent framework, including standard cell compliance and
detailed placement to enable TPL friendly design. Considering TPL constraints
during early design stages, such as standard cell compliance, improves the
layout decomposability. With the pre-coloring solutions of standard cells, we
present a TPL aware detailed placement, where the layout decomposition and
placement can be resolved simultaneously. Our experimental results show that,
with negligible impact on critical path delay, our framework can resolve the
conflicts much more easily, compared with the traditional physical design flow
and followed layout decomposition
L-Shape based Layout Fracturing for E-Beam Lithography
Layout fracturing is a fundamental step in mask data preparation and e-beam
lithography (EBL) writing. To increase EBL throughput, recently a new L-shape
writing strategy is proposed, which calls for new L-shape fracturing, versus
the conventional rectangular fracturing. Meanwhile, during layout fracturing,
one must minimize very small/narrow features, also called slivers, due to
manufacturability concern. This paper addresses this new research problem of
how to perform L-shaped fracturing with sliver minimization. We propose two
novel algorithms. The first one, rectangular merging (RM), starts from a set of
rectangular fractures and merges them optimally to form L-shape fracturing. The
second algorithm, direct L-shape fracturing (DLF), directly and effectively
fractures the input layouts into L-shapes with sliver minimization. The
experimental results show that our algorithms are very effective
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