69 research outputs found
LLR-based Successive Cancellation List Decoding of Polar Codes
We present an LLR-based implementation of the successive cancellation list (SCL) decoder. To this end, we associate each decoding path with a metric which (i) is a monotone function of the path’s likelihood and (ii) can be computed efficiently from the channel LLRs. The LLR-based formulation leads to a more efficient hardware implementation of the decoder compared to the known log-likelihood based implementation. Synthesis results for an SCL decoder with block-length of N = 1024 and list sizes of L = 2 and L = 4 confirm that the LLR-based decoder has considerable area and operating frequency advantages in the orders of 50% and 30%, respectively
On Metric Sorting for Successive Cancellation List Decoding of Polar Codes
We focus on the metric sorter unit of successive cancellation list decoders
for polar codes, which lies on the critical path in all current hardware
implementations of the decoder. We review existing metric sorter architectures
and we propose two new architectures that exploit the structure of the path
metrics in a log-likelihood ratio based formulation of successive cancellation
list decoding. Our synthesis results show that, for the list size of ,
our first proposed sorter is faster and smaller than existing
sorters, while for smaller list sizes, our second sorter has a higher delay in
return for up to reduction in the area.Comment: To be presented in 2015 IEEE International Symposium on Circuits and
Systems (ISCAS'2015
An Implementation of List Successive Cancellation Decoder with Large List Size for Polar Codes
Polar codes are the first class of forward error correction (FEC) codes with
a provably capacity-achieving capability. Using list successive cancellation
decoding (LSCD) with a large list size, the error correction performance of
polar codes exceeds other well-known FEC codes. However, the hardware
complexity of LSCD rapidly increases with the list size, which incurs high
usage of the resources on the field programmable gate array (FPGA) and
significantly impedes the practical deployment of polar codes. To alleviate the
high complexity, in this paper, two low-complexity decoding schemes and the
corresponding architectures for LSCD targeting FPGA implementation are
proposed. The architecture is implemented in an Altera Stratix V FPGA.
Measurement results show that, even with a list size of 32, the architecture is
able to decode a codeword of 4096-bit polar code within 150 us, achieving a
throughput of 27MbpsComment: 4 pages, 4 figures, 4 tables, Published in 27th International
Conference on Field Programmable Logic and Applications (FPL), 201
On Path Memory in List Successive Cancellation Decoder of Polar Codes
Polar code is a breakthrough in coding theory. Using list successive
cancellation decoding with large list size L, polar codes can achieve excellent
error correction performance. The L partial decoded vectors are stored in the
path memory and updated according to the results of list management. In the
state-of-the-art designs, the memories are implemented with registers and a
large crossbar is used for copying the partial decoded vectors from one block
of memory to another during the update. The architectures are quite area-costly
when the code length and list size are large. To solve this problem, we propose
two optimization schemes for the path memory in this work. First, a folded path
memory architecture is presented to reduce the area cost. Second, we show a
scheme that the path memory can be totally removed from the architecture.
Experimental results show that these schemes effectively reduce the area of
path memory.Comment: 5 pages, 6 figures, 2 table
Improved Successive Cancellation Flip Decoding of Polar Codes Based on Error Distribution
Polar codes are a class of linear block codes that provably achieves channel
capacity, and have been selected as a coding scheme for generation
wireless communication standards. Successive-cancellation (SC) decoding of
polar codes has mediocre error-correction performance on short to moderate
codeword lengths: the SC-Flip decoding algorithm is one of the solutions that
have been proposed to overcome this issue. On the other hand, SC-Flip has a
higher implementation complexity compared to SC due to the required
log-likelihood ratio (LLR) selection and sorting process. Moreover, it requires
a high number of iterations to reach good error-correction performance. In this
work, we propose two techniques to improve the SC-Flip decoding algorithm for
low-rate codes, based on the observation of channel-induced error
distributions. The first one is a fixed index selection (FIS) scheme to avoid
the substantial implementation cost of LLR selection and sorting with no cost
on error-correction performance. The second is an enhanced index selection
(EIS) criterion to improve the error-correction performance of SC-Flip
decoding. A reduction of in the implementation cost of logic elements
is estimated with the FIS approach, while simulation results show that EIS
leads to an improvement on error-correction performance improvement up to
dB at a target FER of .Comment: This version of the manuscript corrects an error in the previous
ArXiv version, as well as the published version in IEEE Xplore under the same
title, which has the DOI:10.1109/WCNCW.2018.8368991. The corrections include
all the simulations of SC-Flip-based and SC-Oracle decoders, along with
associated comments in-tex
Successive Cancellation List Polar Decoder using Log-likelihood Ratios
Successive cancellation list (SCL) decoding algorithm is a powerful method
that can help polar codes achieve excellent error-correcting performance.
However, the current SCL algorithm and decoders are based on likelihood or
log-likelihood forms, which render high hardware complexity. In this paper, we
propose a log-likelihood-ratio (LLR)-based SCL (LLR-SCL) decoding algorithm,
which only needs half the computation and storage complexity than the
conventional one. Then, based on the proposed algorithm, we develop
low-complexity VLSI architectures for LLR-SCL decoders. Analysis results show
that the proposed LLR-SCL decoder achieves 50% reduction in hardware and 98%
improvement in hardware efficiency.Comment: accepted by 2014 Asilomar Conference on Signals, Systems, and
Computer
A Randomized Construction of Polar Subcodes
A method for construction of polar subcodes is presented, which aims on
minimization of the number of low-weight codewords in the obtained codes, as
well as on improved performance under list or sequential decoding. Simulation
results are provided, which show that the obtained codes outperform LDPC and
turbo codes.Comment: Accepted to ISIT 2017 Formatting change
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