Study of Tantalum nitride diffusion barrier films for coppper interconnect technology

As technology progressed to ultra - large scale integration leading to smaller and smaller devices, there are continuous challenges in the fields of materials, processes and circuit designs. Copper is the interconnect material of choice because of its low electrical resistivity and high electromigration resistance. However, copper is quite mobile in silicon at elevated temperatures. Therefore, to prevent the diffusion of copper into silicon, a diffusion barrier layer that has fewer grain boundaries, good adhesion to Si and Si02, high thermal and electrical stability with respect to Cu is necessary. Tantalum nitride compounds have been investigated as potential barrier materials. TaN has a very high melting point of 2950C. It is thermodynamically stable with respect to Cu and has good adhesion to the substrate. It has a dense microstructure and shows good resistance to heavy mobility of Cu in Si and has electrical stability at temperatures upto 750 C. The diffusion barrier properties of Ta and its nitrides for copper metallization at RIT have been investigated. The TaNx films were reactively sputter deposited on Si02 substrates at various N2/AJ- ratios. The influence of nitrogen partial pressure on the electrical and structural properties of the films is studied. It has been observed that as deposited pure Ta is tetragonal, which becomes bcc-Ta with small increase in N2 flow to 5% of the sputtering gas mixture. When the nitrogen flow is increased from 12 up to 20%, amorphous and a mixture of amorphous and crystalline Ta2N phase is formed. The amorphous phase crystallizes when annealed to higher temperatures. An fee- TaN phase is formed at N2 flow of 30%. At higher concentrations of N2; nitrogen rich compounds like Ta5N6, Ta3N5 are formed. During backend semiconductor processing, both Cu and TaN films are subjected to various annealing treatments in N2, 02, and Ar at relatively high temperatures. Since these treatments influence the stability of the metallization it was important to establish the effect of the ambients on the integrity of the copper interconnect. The Cu/TaN/Si02 films were annealed to various temperatures up to 600 C in N2, Ar ambients for 20 min and the thermal stability and barrier effectiveness of the films was studied. Annealing the films to temperatures above 500 C cause de-lamination of films at the Cu/TaN interface, which is attributed to the formation of copper oxides with a high density of voids. This was observed by XRD analyis and SEM. RBS spectra showed diffusion of tantalum into the surface of copper at temperatures ~ 500 to 600 C. Therefore we can conclude that cubic TaN films act as stable barrier films up to 500 C in an inert ambient

Flat-plate solar array project. Volume 5: Process development

The goal of the Process Development Area, as part of the Flat-Plate Solar Array (FSA) Project, was to develop and demonstrate solar cell fabrication and module assembly process technologies required to meet the cost, lifetime, production capacity, and performance goals of the FSA Project. R&D efforts expended by Government, Industry, and Universities in developing processes capable of meeting the projects goals during volume production conditions are summarized. The cost goals allocated for processing were demonstrated by small volume quantities that were extrapolated by cost analysis to large volume production. To provide proper focus and coverage of the process development effort, four separate technology sections are discussed: surface preparation, junction formation, metallization, and module assembly

Porous Low-Dielectric-Constant Material for Semiconductor Microelectronics

To provide high speed, low dynamic power dissipation, and low cross-talk noise for microelectronic circuits, low-dielectric-constant (low-k) materials are required as the inter- and intra-level dielectric (ILD) insulator of the back-end-of-line interconnects. Porous low-k materials have low-polarizability chemical compositions and the introducing porosity in the film. Integration of porous low-k materials into microelectronic circuits, however, poses a number of challenges because the composition and porosity affected the resistance to damage during integration processing and reduced the mechanical strength, thereby degrading the properties and reliability. These issues arising from porous low-k materials are the subject of the present chapter

Photoemission studies on the efficacy of self-assembled monolayers (SAMs) for use in transistor interconnect applications

The thesis explores the effectiveness of incorporating amino terminated self-assembled monolayers (SAMs) into several different aspects of the back-end-of-line (BEOL) process for integrated circuit (IC) fabrication . SAMs are essentially two-dimensional nanomolecular assemblies which can display large scale ordering via weak Van der Waals interactions, when deposited on a surface. In this study SAMs are considered for four main applications (i) as a pore sealant for porous dielectrics, (ii) as an adhesion promoter between copper and SiO2, (iii) as a blocker for selective area atomic layer deposition (ALD) and (iv) as a sacrificial layer in the novel electroless deposition (ELD) of cobalt. From a pore sealing perspective, in-situ x-ray photoelectron spectroscopy (XPS) studies have shown that a manganese silicate layer is formed when a thin film of manganese is deposited and annealed on SAM terminated SiO2 and spin-on glass substrates. The presence of a silicate implies that the manganese can diffuse through the SAM and form a chemically stable barrier which could inhibit copper infiltration into the dielectric. In a separate study, XPS analysis of ultra-thin copper films (~0.5nm) deposited on three differently terminated SAMs suggests that amino terminated SAMs offer significant benefits in terms of both the nucleation and adhesion of copper overlayers on dielectric surfaces. A subsequent in-situ XPS study of the effects of atomic oxygen treatments of SAM terminated dielectric substrates displayed that highly controlled stepwise removal of the SAM could be routinely achieved which has significance for the understanding the oxidation cycle in the ALD growth of metal oxides on SAM terminated substrates. Finally, the role of SAMs in cobalt interconnect electroless deposition (ELD) has been characterised by hard x-ray photoelectron spectroscopy (HAXPES) in order to understand the optimized process to fabricate these interconnect structures

Growth and chemical characterisation studies of Mn silicate barrier layers on SiO2 and CDO

This thesis investigates the suitability of manganese silicate (MnSiO3) as a possible copper interconnect diffusion barrier layer on both a 5.4 nm thick thermally grown SiO2 and a low dielectric constant carbon doped oxide (CDO), with the focus of understanding the barrier formation process. The self forming nature of this diffusion barrier layer resulting from the chemical interaction of deposited Mn with the insulating substrate has potential application in future generations of copper interconnect technologies as they are significantly thinner than the conventional deposited barrier layers. The principle technique used to study the interface chemistry resulting from the interaction of deposited manganese with the insulating substrates to form a MnSiO3 layer was x-ray photoelectron spectroscopy (XPS). Transmission electron microscopy (TEM) measurements provided information on the structure of the barrier layers which could be correlated with the XPS results. Significant differences in the extent of the interface interaction which resulted in the formation of the MnSiO3 barrier layer were found to depend on whether the deposited Mn was partially oxidised. The studies performed on the 5.4 nm thermally grown SiO2 confirmed that the growth of the MnSiO3 resulted in a corresponding reduction in the SiO2 layer thickness. Interactions between residual metallic Mn and subsequently deposited copper layers were also investigated and showed that in order to reduce the width of the barrier layer, it was preferable that all the deposited Mn was fully incorporated into the silicate. TEM measurements were also used to investigate thicker thermally deposited Mn/Cu heterostructures on SiO2 which were subsequently annealed in order to study the diffusion interactions between copper and manganese. The formation of Mn silicate layers on low dielectric constant carbon doped oxide (CDO) was also investigated and compared with the formation characteristics on the thermally grown SiO2

A study of the Si3N4/Cu/Ta thin film systems for dual damascene technology

Master'sMASTER OF ENGINEERIN

Effects of scaling on microstructure evolution of Cu nanolines and impact on electromigration reliability

textScaling can significantly degrade the electromigration (EM) lifetime for Cu interconnects, raising serious reliability concerns. Different methods have emerged to enhance the EM resistance of Cu by suppressing the interface diffusion (the historically fastest diffusion path), notably using CoWP metal cap and Mn alloying. With further scaling of Cu interconnects, EM reliability becomes increasingly complex due to changes in Cu microstructure. In ultra-fine Cu lines a large population of small grains mix with bamboo-type grains, resulting in an additional contribution of grain boundary diffusion to EM degradation. With the interface diffusion suppressed by CoWP or Mn alloying, the grain structure effect becomes even more important. The objective of this study is to investigate the EM reliability of ultra-fine Cu interconnects, focusing on the scaling effect on grain structure and mass transport. First, the detailed microstructure information of Cu interconnects down to the 22 nm node was analyzed using a transmission electron microscope (TEM)-based high resolution diffraction technique. A dominant sidewall growth of {111} grains was observed for 70 nm Cu lines (45 nm node), reflecting the importance of interfacial energy in controlling grain growth. The strength of the {111} texture was found to significantly increase as line width was reduced to 40 nm (22 nm node), while the length fraction of coherent twin boundaries was reduced to ~1%. Secondly, the results from microstructure together with the deduced interfacial and grain boundary diffusivities were used to identify flux divergent sites for void formation and to analyze the grain structure effect on EM statistics using a microstructure-based kinetic model. Finally, based on the analysis of Cu grain structure evolution with downscaling, the scaling behavior of EM drift velocity was investigated for Cu interconnects with CoWP capping and Mn alloying. This enables us to project the EM lifetime and statistics for future technology nodes. The Mn alloying effect on mass transport in combination of grain structure control was found to provide an effective means to improve EM reliability especially with further scaling. In summary, this study establishes a correlation between the microstructure of Cu nanolines, void formation kinetics, and EM statistics.Mechanical Engineerin

Carbon Nanotube Interconnects for End-of-Roadmap Semiconductor Technology Nodes

Advances in semiconductor technology due to aggressive downward scaling of on-chip feature sizes have led to rapid rises in resistivity and current density of interconnect conductors. As a result, current interconnect materials, Cu and W, are subject to performance and reliability constraints approaching or exceeding their physical limits. Therefore, alternative materials such as nanocarbons, metal silicides, and Ag nanowires are actively considered as potential replacements to meet such constraints. Among nanocarbons, carbon nanotube (CNT) is among the leading replacement candidate for on-chip interconnect vias due to its high aspect-ratio nanostructure and superior currentcarrying capacity to those of Cu, W, and other potential candidates. However, contact resistance of CNT with metal is a major bottleneck in device functionalization. To meet the challenge posed by contact resistance, several techniques are designed and implemented. First, the via fabrication and CNT growth processes are developed to increase the CNT packing density inside via and to ensure no CNT growth on via sidewalls. CNT vias with cross-sections down to 40 nm 40 nm are fabricated, which have linewidths similar to those used for on-chip interconnects in current integrated circuit manufacturing technology nodes. Then the via top contact is metallized to increase the total CNT area interfacing with the contact metal and to improve the contact quality and reproducibility. Current-voltage characteristics of individual fabricated CNT vias are measured using a nanoprober and contact resistance is extracted with a first-reported contact resistance extraction scheme for 40 nm linewidth. Based on results for 40 nm and 60 nm top-contact metallized CNT vias, we demonstrate that not only are their current-carrying capacities two orders of magnitude higher than their Cu and W counterparts, they are enhanced by reduced via resistance due to contact engineering. While the current-carrying capacities well exceed those projected for end-of-roadmap technology nodes, the via resistances remain a challenge to replace Cu and W, though our results suggest that further innovations in contact engineering could begin to overcome such challenge

Low-cost solar array project and Proceedings of the 14th Project Integration Meeting

Activities are reported on the following areas: project analysis and integration; technology development in silicon material, large area sheet silicon, and encapsulation; production process and equipment development; and engineering and operations, and the steps taken to integrate these efforts. Visual materials presented at the project Integration Meeting are included

Surface chemistry considerations for enhanced vapor deposition of metals

textElectrolessly deposited CoWP capping layers have been demonstrated to effectively reduce electromigration of Cu at the interconnect/dielectric-barrier cap interface while reducing resistivity relative to SiCN. However, as device dimensions scale, the need for alternative methods for the selective deposition of sub-5 nm, ultrathin, conformal Co capping layers is apparent. To develop methods for area-selective atomic layer deposition (AS-ALD) of Co caps for next-generation Cu interconnects, the ALD behavior of bis(N-tert-butyl-N’-ethylpropionamidinato) cobalt(II) (CoAMD) is evaluated on Cu, SiO₂, and a porous low-k ( ~2.6) dielectric, CDO. The first and second ALD half reactions of CoAMD on the respective substrates is evaluated with H₂ coreactant by adsorbing the precursor on the substrates under ALD cycling conditions at 265 °C with and without coreactant exposure. The adsorption studies indicate that CoAMD preferentially deposits most on Cu and least on CDO. Further, CoAMD, like other amidinate precursors, readily dissociates on the Cu transition metal surface but the ultimate per-cycle coverage is self-limited by the slow desorption of amidinate ligands and fragments from the Cu surface. Co films deposited by ALD from CoAMD on Cu at 265 °C indicate that Co burrows into the lower energy Cu surface as the film grows in order to reduce the free surface energy. The Cu remains as a surfactant-like layer on the topmost Co surface up to film thicknesses of at least 16 nm. Moreover, considerable intermixing at the Co/Cu interface and Cu concentration several nm into the Co films are observed indicating high surface mobility of the two materials and Cu diffusion at polycrystalline Co grain boundaries. Finally, employing low-tempurature ALD and selectively passivating the dielectric surfaces with OH targeting passivants leads to enhanced selectivity of CoAMD for deposition on Cu versus SiO₂ and CDO. Depositing Co from CoAMD on Cu and CDO at 165 °C after 500 kTorr-s exposure to trimethylchlorosilane at 50 °C leads to a 30:1 preference for Co accumulation on Cu, a twelve times improvement compared to deposition on cleaned Cu and CDO at 265 °C.Chemical Engineerin