Baseband Data Handling System Using LEON3FT Processor

The data handling system is used to receive the data from the payloads of the satellite and format the data into suitable form so that it can be successfully received at the ground station. Data handling system consists of payload interface unit, preprocessor unit, data compression unit, data encryption unit, and channel coding and frame formatter. Till now, data handling systems were developed with the help of FPGAs. The current project involves the development of on board data handling system based on LEON3FT processor. Processor provides the advantages of reduced hardware complexity, programmability and computational performance

A SiGe BiCMOS LVDS Driver for Space-Borne Applications

When designing an integrated circuit for use during an interstellar mission, certain precautions must be made. The electronics on any off-earth mission will be exposed to wide temperature swings and harmful radiation due to being outside of the Earth’s protective ionosphere. It is crucial that any data path present be immune to these detrimental effects. The introduction of galactic radiation can not only cause the onboard electronics to fail due to device degradation and single event latchup but can also lead to background radiation being coupled into the signal path as unwanted noise, degrading the signal to noise ratio. Unwanted noise can cause total failure by increasing the noise level and decreasing the signal to noise ratio below one or can cause errors such as single event upsets. The wide temperature swing can cause device degradation and eventually failure. This issue is commonly mitigated by the introduction of an environment chamber but such an enclosure adds unnecessary mass and typically requires a large amount of current to effectively keep the electronics in an Earth-like temperature. The large current implies high power dissipation which is an unnecessary strain on the battery and can shorten the lifetime of a mission where every kilowatt-hour is crucial to success. The solution to these two non-trivial obstacles is to design an electronic circuit such that it can operate in a wide range of temperatures and can withstand the galactic radiation that it will inevitably encounter during its mission’s lifetime. The following thesis will document the design, simulation, and testing of a Si-Ge Bi-CMOS low voltage differential signal driver for space borne applications

A high speed Tri-Vision system for automotive applications

Purpose: Cameras are excellent ways of non-invasively monitoring the interior and exterior of vehicles. In particular, high speed stereovision and multivision systems are important for transport applications such as driver eye tracking or collision avoidance. This paper addresses the synchronisation problem which arises when multivision camera systems are used to capture the high speed motion common in such applications. Methods: An experimental, high-speed tri-vision camera system intended for real-time driver eye-blink and saccade measurement was designed, developed, implemented and tested using prototype, ultra-high dynamic range, automotive-grade image sensors specifically developed by E2V (formerly Atmel) Grenoble SA as part of the European FP6 project – sensation (advanced sensor development for attention stress, vigilance and sleep/wakefulness monitoring). Results : The developed system can sustain frame rates of 59.8 Hz at the full stereovision resolution of 1280 × 480 but this can reach 750 Hz when a 10 k pixel Region of Interest (ROI) is used, with a maximum global shutter speed of 1/48000 s and a shutter efficiency of 99.7%. The data can be reliably transmitted uncompressed over standard copper Camera-Link® cables over 5 metres. The synchronisation error between the left and right stereo images is less than 100 ps and this has been verified both electrically and optically. Synchronisation is automatically established at boot-up and maintained during resolution changes. A third camera in the set can be configured independently. The dynamic range of the 10bit sensors exceeds 123 dB with a spectral sensitivity extending well into the infra-red range. Conclusion: The system was subjected to a comprehensive testing protocol, which confirms that the salient requirements for the driver monitoring application are adequately met and in some respects, exceeded. The synchronisation technique presented may also benefit several other automotive stereovision applications including near and far-field obstacle detection and collision avoidance, road condition monitoring and others.Partially funded by the EU FP6 through the IST-507231 SENSATION project.peer-reviewe

The CMS Global Calorimeter Trigger Hardware Design

An alternative design for the CMS Global Calorimeter Trigger (GCT) is being implemented. The new design adheres to all the CMS specifications regarding interfaces and functional requirements of the trigger systems. The design is modular, compact, and utilizes proven components. Functionality has been partitioned to allow commissioning in stages corresponding to the different capabilities being made operational. The functional breakdown and hardware platform is presented and discussed. A related paper discusses the firmware required to implement the GCT functionality

High-Speed Low-Voltage Line Driver for SerDes Applications

The driving factor behind this research was to design & develop a line driver capable of meeting the demanding specifications of the next generation of SerDes devices. In this thesis various line driver topologies were analysed to identify a topology suited for a high-speed low-voltage operating environment. This thesis starts of by introducing a relatively new high-speed communication Device called SerDes. SerDes is used in wired chip-to-chip communications and operates by converting a parallel data stream in a serial data stream that can be then transmitted at a higher bit rate, existing SerDes devices operate up to 12.5Gbps. A matching SerDes device at the destination will then convert the serial data stream back into a parallel data stream to be read by the destination ASIC. SerDes typically uses a line driver with a differential output. Using a differential line driver increases the resilience to outside sources of noise and reduces the amount of EM radiation produced by transmission. The focus of this research is to design and develop a line driver that can operate at 40Gbps and can function with a power supply of less than IV. This demanding specification was decided to be an accurate representation of future requirements that a line driver in a SerDes device will have to conform to. A suitable line driver with a differential output was identified to meet the demanding specifications and was modified so that it can perfonn an equalisation technique called pre-distortion. Two variations of the new topology were outlined and a behavioural model was created for both using Matlab Simulink. The behavioural model for both variants proved the concept, however only one variant maintained its perfomance once the designs were implemented at transistor level in Cadence, using a 65nm CMOS technology provided by Texas Instruments. The final line driver design was then converted into a layout design, again using Cadence, and RC parasitics were extracted to perfom a post-layout simulation. The post layout simulation shows that the novel line driver can operate at 40Gbps with a power supply of 1 V - O.8V and has a power consumption of 4.54m W /Gbps. The Deterministic Jitter added by the line driver is 12.9ps

A complete system for controlling and monitoring the timing of the LHCb experiment

The LHCb experiment at CERN will study the results of the production of B/antiB in the LHC accelerator mesons with the higher precision ever. It is vital that the experiment is able to record sub-detectors signals at the optimal detector efficiency, referring to the right collision occurring in the LHC ring, and that those signals are stable, clean and reliable. The solution is the development of a complete system to centrally time align and at the same time to monitor the timing of the whole experiment. An electronics custom-made acquisition board, called Beam Phase and Intensity Monitor (BPIM), has the main aim to monitor the beam processing a bipolar signal coming from a dedicated Beam Pick-Up detector, sitting along the LHC ring and whose signal is a clear representation of the bunches of protons. The BPIM is then able to integrate the intensity of the beam and at the same time to compare the phase of the bunch signal with the clock coming from the timing distribution system as well as the phase of the orbit signal with the signal generated from the first beam bunch. The principal applications of the BPIM are to determine the position of the orbit signal locally, to monitor bunch-by-bunch the clock phase with respect to the bunch passing through the detector, to have a clear structure of the beam injected, to determine the exact trigger conditions for sampling events in the detector, to determine the exact trigger conditions for significative events of not, checking whether the detector samples a bunch with protons (or lead ions) or an empty bunch, to produce an empty crossing veto for the sampled events whenever a bunch is absent in the expected location, to have a relative measure of the intensities of bunch, to have instantaneaous information about the presence/absence of beam, and, not less important, to search for ghost bunches. The board is paired with the RF2TTC system developed by the LHC group and whose aim is to control, clean, convert and transmit the bunch clock (~40 MHz) and the orbit clock (~11 KHz) to the the whole experiment. A complete user-friendly interface system, developed using the SCADA software PVSS II with the Distributed Information Management (DIM) system as communication protocol, allows to control and monitor real-time the available information

Camera-link and synchronism in automotive multi-vision systems

Cameras are excellent ways of non-invasively monitoring the interior and exterior of vehicles. The motivations for cabin monitoring are largely safety related and include occupant detection, occupant classification, and driver vigilance/drowsiness monitoring. Exterior vehicular monitoring has wider motivations including road surface condition monitoring, lane-departure warning systems, blind spot warning, collision warning/mitigation/avoidance, vehicle security, traffic sign detection and adaptive cruise control. The large number of cameras envisaged, necessitates the development of a novel, high performance methodology for interfacing several cameras to a central processing hub over a single lightweight cable whilst preserving a high degree of synchronicity between stereovision or multivision sets. Such a solution, which is also backward compatible with the Camera-Link® standard, is thus presented. This results in substantial cabling, weight and cost savings while simultaneously guaranteeing superior performance. A stereovision design and implementation is presented that makes use of prototype, ultra-high dynamic range, automotive-grade image sensors developed by ATMEL Grenoble SA as part of the European FP6 Project - SENSATION (Advanced Sensor Development for Attention, Stress, Vigilance and Sleep/Wakefulness Monitoring).European FP6 Project - SENSATION (Advanced Sensor Development for Attention, Stress, Vigilance and Sleep/Wakefulness Monitoring)peer-reviewe

Data Acquisition System for Quality Tests of the ATLAS Muon Endcap Trigger Chambers

The ATLAS The Collaboration is building a general-purpose pp detector which is design to exploit the full discovery potential of the high energy proton-proton interaction Large Hadron Collider (LHC) at CERN. The LHC offers a large range of physics opportunities, among which the origin of mass at the electroweak scale is a major focus of interest for ATLAS. The detector optimization is therefore guided by physics issues such a sensitivity to the largest possible Higgs mass range. The Thin Gap Chambers (TGCs) are detectors designed to detect the high transverse momentum muons in the endcaps of the ATLAS detector. The short response time of the TGCs makes it an ideal trigger system for selecting interesting events in the highly packed environment of the LHC accelerator. The TGCs are designed and built in Weizmann Institute and are tested at the Tel-Aviv University and at the Technion. The subject of this dissertation is the design and operation of the data acqusition system, which serves to automatize the procedure of testing the performance of the TGC detector, before are to be installed in the ATLAS experiment

Belle II Technical Design Report

The Belle detector at the KEKB electron-positron collider has collected almost 1 billion Y(4S) events in its decade of operation. Super-KEKB, an upgrade of KEKB is under construction, to increase the luminosity by two orders of magnitude during a three-year shutdown, with an ultimate goal of 8E35 /cm^2 /s luminosity. To exploit the increased luminosity, an upgrade of the Belle detector has been proposed. A new international collaboration Belle-II, is being formed. The Technical Design Report presents physics motivation, basic methods of the accelerator upgrade, as well as key improvements of the detector.Comment: Edited by: Z. Dole\v{z}al and S. Un