Hardware/Software Codesign

The current state of the art technology in integrated circuits allows the incorporation of multiple processor cores and memory arrays, in addition to application specific hardware, on a single substrate. As silicon technology has become more advanced, allowing the implementation of more complex designs, systems have begun to incorporate considerable amounts of embedded software [3]. Thus it becomes increasingly necessary for the system designers to have knowledge on both hardware and software to make efficient design tradeoffs. This is where hardware/software codesign comes into existence

Hardware/Software Co-design of Communication Protocols

An important aspect in providing high performance distributed systems such as multimedia systems is the combined use of hardware and software in the end systems. System design techniques should allow hardware/software co-design to integrate both means of implementation. In this paper, we show how the standardized formal language Estelle can be used to facilitate co-design. The system will first be designed in Estelle. At the point in time of final decision on which parts to implement in software and which in hardware, the original specification will be split into several partial specifications. The software parts are translated into C code, while the hardware parts are translated into VHDL code for further analysis and development. We present a tool environment which supports the protocol developer in the design and implementation process. A simple Video-on-Demand example shows the usefulness of the tool environment

Computer Assisted Design and Integration of FPGA Accelerators in Aerospace Systems

The integration of Field Programmable Gate Arrays (FPGAs) in an aerospace system allows to improve its efficiency and its flexibility thanks to their programmability. To exploit these devices, the designer has to identify the functionalities that have to be executed on them and provide their implementation by means of Hardware Description Languages. Generating these descriptions for a software developer could be a very difficult task because of the different programming paradigms of software programs and hardware descriptions. To facilitate the developer in this activity, High Level Synthesis techniques have been developed aiming at (semi-)automatically generating hardware implementations of specifications written in high level languages (e.g., C). State of the art tools implementing such methodologies have not been designed for the integration with aerospace systems design flows, so significant adaptations could be required to the designer for integrating the hardware implementations with the rest of the design solution. In this paper the integration of a High Level Synthesis design flow in the TASTE framework (http://taste.tuxfamily.org) is presented. TASTE is a set of freely available tools for the development of real time embedded systems developed by the European Space Agency together with a set of its industrial partners. This framework allows to integrate specifications described in different languages (e.g., C, ADA, Simulink, SDL) by means of formal languages (AADL and ASN.1) and to early verify the correctness of the produced solutions. TASTE has been extended with Bambu (http://panda.dei.polimi.it), a tool for the High Level Synthesis developed at Politecnico di Milano. In this way the TASTE users have the possibility to specify which functionalities, provided by means of high level languages such C, have to be implemented in hardware on the FPGA without having to directly provide the hardware implementations. Thanks to the integration of the High Level Synthesis tool indeed, the framework is able not only to produce the hardware implementations, but also to integrate them in the rest of the aerospace system by automatically generating the whole architecture to be implemented on the FPGA. This architecture contains not only the implementation of the hardware accelerators, but also of the components required to transfer the data from and to the rest of the system and to correctly manage their size and endianness. The application of the extended framework to a real case study shows its effective usability

Élaboration d'un modèle d'abstraction des communications point-à-point pour une plateforme (SOC) multiprocesseur hétérogène

Les systèmes embarqués modernes -- Problématique -- Les communications dans un système-sur-puce -- Les modèles de communication pour MPSoC -- Les architectures de communication -- Abstraction des communications à haut niveau -- Génération des interfaces logiciel-matériel -- Une plateforme virtuelle hétérogène et extensible pour SPACE -- La plateforme CoreConnect d'IBM implémentée par Xilinx -- Le PowerPC405FX -- Intégration de l'ISS du PowerPC à SpaceLib -- DirectLink : Abstraction des communications point-à -point dans la plateforme virtuelle SPACE -- Paradigme du DirectLink -- Méthodologie -- Spécification des interfaces -- Connections module/module HW-HW -- Connexions module/module HW/SW ou SW/HW -- Connexions module/module SW/SW -- Design des composants SpaceLib -- Implications au niveau de la pile logicielle -- Abstraction du DirectLink dans SPACE -- Analyse, performances et discussion -- Validation du paradigme DirectLink -- Technique d'analyse des performances -- Performances du DirectLink -- Impact sur l'utilisation des ressources matérielles -- Accélération d'une application dans SPACE avec le DirectLink -- Extensibilité du paradigme à d'autres plateformes -- Comparaison avec d'autres travaux -- Améliorations suggérées à l'architecture de communication SPACE

Timing verification in transaction modeling

Les systèmes Matériels/Logiciels deviennent indispensables dans tous les aspects de la vie quotidienne. La présence croissante de ces systèmes dans les différents produits et services incite à trouver des méthodes pour les développer efficacement. Mais une conception efficace de ces systèmes est limitée par plusieurs facteurs, certains d'entre eux sont: la complexité croissante des applications, une augmentation de la densité d'intégration, la nature hétérogène des produits et services, la diminution de temps d’accès au marché. Une modélisation transactionnelle (TLM) est considérée comme un paradigme prometteur permettant de gérer la complexité de conception et fournissant des moyens d’exploration et de validation d'alternatives de conception à des niveaux d’abstraction élevés. Cette recherche propose une méthodologie d’expression de temps dans TLM basée sur une analyse de contraintes temporelles. Nous proposons d'utiliser une combinaison de deux paradigmes de développement pour accélérer la conception: le TLM d'une part et une méthodologie d’expression de temps entre différentes transactions d’autre part. Cette synergie nous permet de combiner dans un seul environnement des méthodes de simulation performantes et des méthodes analytiques formelles. Nous avons proposé un nouvel algorithme de vérification temporelle basé sur la procédure de linéarisation des contraintes de type min/max et une technique d'optimisation afin d'améliorer l'efficacité de l'algorithme. Nous avons complété la description mathématique de tous les types de contraintes présentées dans la littérature. Nous avons développé des méthodes d'exploration et raffinement de système de communication qui nous a permis d'utiliser les algorithmes de vérification temporelle à différents niveaux TLM. Comme il existe plusieurs définitions du TLM, dans le cadre de notre recherche, nous avons défini une méthodologie de spécification et simulation pour des systèmes Matériel/Logiciel basée sur le paradigme de TLM. Dans cette méthodologie plusieurs concepts de modélisation peuvent être considérés séparément. Basée sur l'utilisation des technologies modernes de génie logiciel telles que XML, XSLT, XSD, la programmation orientée objet et plusieurs autres fournies par l’environnement .Net, la méthodologie proposée présente une approche qui rend possible une réutilisation des modèles intermédiaires afin de faire face à la contrainte de temps d’accès au marché. Elle fournit une approche générale dans la modélisation du système qui sépare les différents aspects de conception tels que des modèles de calculs utilisés pour décrire le système à des niveaux d’abstraction multiples. En conséquence, dans le modèle du système nous pouvons clairement identifier la fonctionnalité du système sans les détails reliés aux plateformes de développement et ceci mènera à améliorer la "portabilité" du modèle d'application.Hardware/Software (Hw/Sw) systems are likely to become essential in all aspects of everyday life. The increasing penetration of Hw/Sw systems in products and services creates a necessity of their efficient development. However, the productive design of these systems is limited by several factors, some of them being the increasing complexity of applications, the increasing degree of integration, the heterogeneous nature of products and services as well as the shrinking of the time-to-market delay. Transaction Level Modeling (TLM) paradigm is considered as one of the most promising simulation paradigms to break down the design complexity by allowing the exploration and validation of design alternatives at high levels of abstraction. This research proposes a timing expression methodology in TLM based on temporal constraints analysis. We propose to use a combination of two paradigms to accelerate the design process: TLM on one hand and a methodology to express timing between different transactions on the other hand. Using a timing specification model and underlining timing constraints verification algorithms can decrease the time needed for verification by simulation. Combining in one framework the simulation and analytical design exploration methods can improve the analytical power of design verification and validation. We have proposed a new timing verification algorithm based on the linearization procedure and an optimization technique to improve its efficiency. We have completed the mathematical representation of all constraint types discussed in the literature creating in this way a unified timing specification methodology that can be used in the expression of a wider class of applications than previously presented ones. We have developed the methods for communication structure exploration and refinement that permitted us to apply the timing verification algorithms in system exploration at different TLM levels. As there are many definitions of TLM and many development environments proposing TLM in their design cycle with several pro and contra, in the context of our research we define a hardware/software (Hw/Sw) specification and simulation methodology which supports TLM in such a way that several modeling concepts can be seen separately. Relying on the use of modern software engineering technologies such as XML, XSLT, XSD, object oriented programming and others supported by the .Net Framework, an approach that makes an intermediate design model reuse possible in order to cope with time-to-market constraint is presented. The proposed TLM design methodology provides a general approach in system modeling that separates various application modeling aspects from system specification: computational models, used in application modeling, supported by the language used for the functional specification and provided by simulator. As a result, in the system model we can clearly identify system functionality without details related to the development platform thereby leading to a better “portability” of the application model

Data Transfers Analysis in Computer Assisted Design Flow of FPGA Accelerators for Aerospace Systems

The integration of Field Programmable Gate Arrays (FPGAs) in an aerospace system improves its efficiency and its flexibility thanks to their programmability, but increases the design complexity. The design flows indeed have to be composed of several steps to fill the gap between the starting solution, which is usually a reference sequential implementation, and the final heterogeneous solution which includes custom hardware accelerators. Among these steps, there are the analysis of the application to identify the functionalities that gain advantages in execution on hardware and the generation of their implementations by means of Hardware Description Languages. Generating these descriptions for a software developer can be a very difficult task because of the different programming paradigms of software programs and hardware descriptions. To facilitate the developer in this activity, High Level Synthesis techniques have been developed aiming at (semi-)automatically generating hardware implementations of specifications written in high level languages (e.g., C). With respect to other embedded systems scenarios, the aerospace systems introduce further constraints that have to be taken into account during the design of these heterogeneous systems. In this type of systems explicit data transfers to and from FPGAs are preferred to the adoption of a shared memory architecture. The first approach indeed potentially improves the predictability of the produced solutions, but the sizes of all the data transferred to and from any devices must be known at design time. Identifying the sizes in presence of complex C applications which use pointers can be a not so easy task. In this paper, a semi-automatic design flow based on the integration of an aerospace design flow, an application analysis technique, and High Level Synthesis methodologies is presented. The initial reference application is analyzed to identify which are the sizes of the data exchanged among the different components of the application. Next, starting from the high level specification and from the results of this analysis, High Level Synthesis techniques are applied to automatically produce the hardware accelerators

An object-based codesign methodology.

The research into Codesign of Hardware and Software stems from the development of embedded systems, on which various systems restrictions are imposed. Typical restrictions can be the overall time (latency) to complete an assigned function and the space/power limits within the system. Although software can be used to undertake most tasks in an embedded system, ASIC (Application Specific Integrated Circuits) hardware components sometimes have to be recruited to meet the system constraints. Designing the restricted embedded system with both software and hardware components in it involves the analysis of not only individual hardware/software components but also their mutual influences. Using co-design principles, the approach is to consider both hardware and software from a coherent viewpoint.This thesis presents the results from our research project in the area of Codesign of Hardware and Software. In this project, we investigated previously published codesign approaches and their methodological supports. The investigation has identified shortcomings and problems with the existing codesign methodologies. A new object-based codesign approach (Co-PARSE) is thus developed in this project, which is supported by successive phases, guidelines, and techniques. This methodology offers a coherent design framework for real-time embedded systems and incorporates the criteria of system performance and hardware cost. Tools have been developed to facilitate the use of the methodology. Within the methodology, a high-level system modeling and specification approach has been developed and formalised in the Co-BSL (Codesign Behavior Specification Language). The means of transforming Co-BSL specifications to C and VHDL implementations is defined, and a library of VHDL components provided. The thesis documents the partitioning approach taken within the methodology and proposes a new multi-layered bus architecture as a basis for more flexible and efficient implementations. A means of simulating the performance characteristics of this architecture under different configurations is provided, and examples of simulation results are presented. A new embedded system (the Radio Data Computing System) is designed and simulated in the Co-PARSE methodology and simulation results analysed. The thesis concludes with an evaluation of the work carried out in the project and proposals for extending the results obtained in future research.The major contributions reported in this thesis can be summarised as follows. First, the unified system specification means has been designed, which is embodied in the Co-BSL. It captures overall dynamic aspects and performance constraints in the system under development. This high-level specification language is independent of implementation and does not bias the designer towards the use of hardware or software components at this early stage. Second, within Co-PARSE, the target architecture of the system under development has been exploited to improve the system performance and at the same time to reduce hardware cost. This novel concept has been realised by the introduction of an asynchronous bus protocol and the multi-layer bus communication structure. Third, in order to evaluate the strength and practicability of the Co-PARSE methodology, an extensive case study has been carried out. The new RDC (Radio Dada Computing) System has been designed in the proposed codesign approach. Codesign phases are subsequently applied and the guidelines and tools that are specially developed in support of the methodology are fully utilized