109 research outputs found
The AXIOM software layers
AXIOM project aims at developing a heterogeneous computing board (SMP-FPGA).The Software Layers developed at the AXIOM project are explained.OmpSs provides an easy way to execute heterogeneous codes in multiple cores. People and objects will soon share the same digital network for information exchange in a world named as the age of the cyber-physical systems. The general expectation is that people and systems will interact in real-time. This poses pressure onto systems design to support increasing demands on computational power, while keeping a low power envelop. Additionally, modular scaling and easy programmability are also important to ensure these systems to become widespread. The whole set of expectations impose scientific and technological challenges that need to be properly addressed.The AXIOM project (Agile, eXtensible, fast I/O Module) will research new hardware/software architectures for cyber-physical systems to meet such expectations. The technical approach aims at solving fundamental problems to enable easy programmability of heterogeneous multi-core multi-board systems. AXIOM proposes the use of the task-based OmpSs programming model, leveraging low-level communication interfaces provided by the hardware. Modular scalability will be possible thanks to a fast interconnect embedded into each module. To this aim, an innovative ARM and FPGA-based board will be designed, with enhanced capabilities for interfacing with the physical world. Its effectiveness will be demonstrated with key scenarios such as Smart Video-Surveillance and Smart Living/Home (domotics).Peer ReviewedPostprint (author's final draft
HPCCP/CAS Workshop Proceedings 1998
This publication is a collection of extended abstracts of presentations given at the HPCCP/CAS (High Performance Computing and Communications Program/Computational Aerosciences Project) Workshop held on August 24-26, 1998, at NASA Ames Research Center, Moffett Field, California. The objective of the Workshop was to bring together the aerospace high performance computing community, consisting of airframe and propulsion companies, independent software vendors, university researchers, and government scientists and engineers. The Workshop was sponsored by the HPCCP Office at NASA Ames Research Center. The Workshop consisted of over 40 presentations, including an overview of NASA's High Performance Computing and Communications Program and the Computational Aerosciences Project; ten sessions of papers representative of the high performance computing research conducted within the Program by the aerospace industry, academia, NASA, and other government laboratories; two panel sessions; and a special presentation by Mr. James Bailey
The AXIOM Software Layers
25siopenPeople and objects will soon share the same digital network for information exchange in a world named as the age of the cyber-physical systems. The general expectation is that people and systems will interact in real-time. This poses pressure onto systems design to support increasing demands on computational power, while keeping a low power envelop. Additionally, modular scaling and easy programmability are also important to ensure these systems to become widespread. The whole set of expectations impose scientific and technological challenges that need to be properly addressed. The AXIOM project (Agile, eXtensible, fast I/O Module) will research new hardware/software architectures for cyber-physical systems to meet such expectations. The technical approach aims at solving fundamental problems to enable easy programmability of heterogeneous multi-core multi-board systems. AXIOM proposes the use of the task-based OmpSs programming model, leveraging low-level communication interfaces provided by the hardware. Modular scalability will be possible thanks to a fast interconnect embedded into each module. To this aim, an innovative ARM and FPGA-based board will be designed, with enhanced capabilities for interfacing with the physical world. Its effectiveness will be demonstrated with key scenarios such as Smart Video-Surveillance and Smart Living/Home (domotics).openAlvarez, C.; Ayguade, E.; Bosch, J.; Bueno, J.; Cherkashin, A.; Filgueras, A.; Jiminez-Gonzalez, D.; Martorell, X.; Navarro, N.; Vidal, M.; Theodoropoulos, D.; Pnevmatikatos, D.; Catani, D.; Oro, D.; Fernandez, C.; Segura, C.; Rodriguez, J.; Hernando, J.; Scordino, C.; Gai, P.; Passera, P.; Pomella, A.; Bettin, N.; Rizzo, A.; Giorgi, R.Alvarez, C.; Ayguade, E.; Bosch, J.; Bueno, J.; Cherkashin, A.; Filgueras, A.; Jiminez-Gonzalez, D.; Martorell, X.; Navarro, N.; Vidal, M.; Theodoropoulos, D.; Pnevmatikatos, D.; Catani, D.; Oro, D.; Fernandez, C.; Segura, C.; Rodriguez, J.; Hernando, J.; Scordino, C.; Gai, P.; Passera, P.; Pomella, A.; Bettin, N.; Rizzo, A.; Giorgi, R
Optimisation des mémoires dans le flot de conception des systÚmes multiprocesseurs sur puces pour des applications de type multimédia
RĂSUMĂ
Les systĂšmes multiprocesseurs sur puce (MPSoC) constituent l'un des principaux moteurs de
la rĂ©volution industrielle des semi-conducteurs. Les MPSoCs jouissent dâune popularitĂ©
grandissante dans le domaine des systĂšmes embarquĂ©s. Leur grande capacitĂ© de parallĂ©lisation Ă
un trÚs haut niveau d'intégration, en font de bons candidats pour les systÚmes et les applications
telles que les applications multimĂ©dia. La consommation dâĂ©nergie, la capacitĂ© de calcul et
lâespace de conception sont les Ă©lĂ©ments dont dĂ©pendent les performances de ce type
dâapplications. La mĂ©moire est le facteur clĂ© permettant dâamĂ©liorer de façon substantielle leurs
performances. Avec lâarrivĂ©e des applications multimĂ©dias embarquĂ©es dans lâindustrie, le
problÚme des gains de performances est vital. La masse de données traitées par ces applications
requiert une grande capacité de calcul et de mémoire. DerniÚrement, de nouveaux modÚles de
programmation ont fait leur apparition. Ces modĂšles offrent une programmation de plus haut
niveau pour rĂ©pondre aux besoins croissants des MPSoCs, dâoĂč la nĂ©cessitĂ© de nouvelles
approches d'optimisation et de placement pour les systÚmes embarqués et leurs modÚles de
programmation.
La conception niveau systĂšme des architectures MPSoCs pour les applications de type
multimĂ©dia constitue un vĂ©ritable dĂ©fi technique. Lâobjectif gĂ©nĂ©ral de cette thĂšse est de relever
ce dĂ©fi en trouvant des solutions. Plus spĂ©cifiquement, cette thĂšse se propose dâintroduire le
concept dâoptimisation mĂ©moire dans le flot de conception niveau systĂšme et dâobserver leur
impact sur différents modÚles de programmation utilisés lors de la conception de MPSoCs. Il
sâagit, autrement dit, de rĂ©aliser lâunification du domaine de la compilation avec celui de la
conception niveau systĂšme pour une meilleure conception globale.
La contribution de cette thĂšse est de proposer de nouvelles approches pour les techniques
d'optimisation mémoire pour la conception MPSoCs avec différents modÚles de programmation.
Nos travaux de recherche concernent l'intĂ©gration des techniques dâoptimisation mĂ©moire dans le
flot de conception de MPSoCs pour différents types de modÚle de programmation. Ces travaux
ont été exécutés en collaboration avec STMicroelectronics.----------ABSTRACT
Multiprocessor systems-on-chip (MPSoC) are defined as one of the main drivers of the
industrial semiconductors revolution. MPSoCs are gaining popularity in the field of embedded
systems. Pursuant to their great ability to parallelize at a very high integration level, they are
good candidates for systems and applications such as multimedia. Memory is becoming a key
player for significant improvements in these applications (i.e. power, performance and area).
With the emergence of more embedded multimedia applications in the industry, this issue
becomes increasingly vital. The large amount of data manipulated by these applications requires
high-capacity calculation and memory. Lately, new programming models have been introduced.
These programming models offer a higher programming level to answer the increasing needs of
MPSoCs. This leads to the need of new optimization and mapping approaches suitable for
embedded systems and their programming models.
The overall objective of this research is to find solutions to the challenges of system level
design of applications such as multimedia. This entails the development of new approaches and
new optimization techniques. The specific objective of this research is to introduce the concept
of memory optimization in the system level conception flow and study its impact on different
programming models used for MPSoCsâ design. In other words, it is the unification of the
compilation and system level design domains.
The contribution of this research is to propose new approaches for memory optimization
techniques for MPSoCsâ design in different programming models. This thesis relates to the
integration of memory optimization to varying programming model types in the MPSoCs
conception flow. Our research was done in collaboration with STMicroelectronics
Survey of Parallel Processing on Big Data
No doubt we are entering the big data epoch. The datasets have gone from small to super large scale, which not only brings us benefits but also some challenges. It becomes more and more difficult to handle them with traditional data processing methods. Many companies have started to invest in parallel processing frameworks and systems for their own products because the serial methods cannot feasibly handle big data problems. The parallel database systems, MapReduce, Hadoop, Pig, Hive, Spark, and Twister are some examples of these products. Many of these frameworks and systems can handle different kinds of big data problems, but none of them can cover all the big data issues. How to wisely use existing parallel frameworks and systems to deal with large-scale data becomes the biggest challenge. We investigate and analyze the performance of parallel processing for big data. We review and analyze various parallel processing architectures and frameworks, and their capabilities for large-scale data. We also present the potential challenges on multiple techniques according to the characteristics of big data. At last, we present possible solutions for those challenges
The Family of MapReduce and Large Scale Data Processing Systems
In the last two decades, the continuous increase of computational power has
produced an overwhelming flow of data which has called for a paradigm shift in
the computing architecture and large scale data processing mechanisms.
MapReduce is a simple and powerful programming model that enables easy
development of scalable parallel applications to process vast amounts of data
on large clusters of commodity machines. It isolates the application from the
details of running a distributed program such as issues on data distribution,
scheduling and fault tolerance. However, the original implementation of the
MapReduce framework had some limitations that have been tackled by many
research efforts in several followup works after its introduction. This article
provides a comprehensive survey for a family of approaches and mechanisms of
large scale data processing mechanisms that have been implemented based on the
original idea of the MapReduce framework and are currently gaining a lot of
momentum in both research and industrial communities. We also cover a set of
introduced systems that have been implemented to provide declarative
programming interfaces on top of the MapReduce framework. In addition, we
review several large scale data processing systems that resemble some of the
ideas of the MapReduce framework for different purposes and application
scenarios. Finally, we discuss some of the future research directions for
implementing the next generation of MapReduce-like solutions.Comment: arXiv admin note: text overlap with arXiv:1105.4252 by other author
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