Embedded DSP Processor Design using Coware Processor Designer and Magma Layout Tool

A Digital Signal Processing (DSP) application can be implemented in a variety of ways. The objective of this project is to design an Embedded DSP Processor. The desired processor is run by an instruction set. Such a processor is called an Application Specific Instruction Set Processor (ASIP). ASIP is becoming essential to convergent System on Chip (SoC) Design. Usually there are two approaches to design an ASIP. One of them is at Register Transfer Level (RTL) and another is at just higher level than RTL and is known as Electronic System Level (ESL). Application Description Languages (ADLs) are becoming popular recently because of its quick and optimal design convergence achievement capability during the design of ASIPs. In this project we first concentrate on the implementation and optimization of an ASIP using an ADL known as Language for Instruction Set Architecture (LISA) and CoWare Processor Designer environment. We have written a LISA 2.0 description of the processor. Given a LISA code, the CoWare Processor Designer (PD) then generates Software Development tools like assembler, disassembler, linker and compiler. A particular application in assembly language to find out the convolution using FIR filter is then run on the processor. Provided that the functionality of the processor is correct, synthesizable RTL for the processor can be generated using Coware Processor Generator. Using the RTL generated, we implemented our processor in the following IC Design technologies: • Semi-Custom IC Design Technology Here, the RTL is synthesized using Magma Blast Create Tool and the final Layout is drawn using Magma Blast Fusion Tool • Programmable Logic Device IC Design Technology Here, the processor is dumped to a Field Programmable Gate Array (FPGA). The FPGA used for this purpose is Xilinx Virtex II Pro