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    A weighted pair graph representation for reconstructibility of Boolean control networks

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    A new concept of weighted pair graphs (WPGs) is proposed to represent a new reconstructibility definition for Boolean control networks (BCNs), which is a generalization of the reconstructibility definition given in [Fornasini & Valcher, TAC2013, Def. 4]. Based on the WPG representation, an effective algorithm for determining the new reconstructibility notion for BCNs is designed with the help of the theories of finite automata and formal languages. We prove that a BCN is not reconstructible iff its WPG has a complete subgraph. Besides, we prove that a BCN is reconstructible in the sense of [Fornasini & Valcher, TAC2013, Def. 4] iff its WPG has no cycles, which is simpler to be checked than the condition in [Fornasini & Valcher, TAC2013, Thm. 4].Comment: 20 pages, 10 figures, accepted by SIAM Journal on Control and Optimizatio

    LOT: Logic Optimization with Testability - new transformations for logic synthesis

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    A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transformations involving EX-OR gates as well as Reed–Muller expansions have been introduced in the synthesis of multilevel circuits. This method is augmented with transformations that specifically enhance random-pattern testability while reducing the area. Testability enhancement is an integral part of our synthesis methodology. Experimental results show that the proposed methodology not only can achieve lower area than other similar tools, but that it achieves better testability compared to available testability enhancement tools such as tstfx. Specifically for ISCAS-85 benchmark circuits, it was observed that EX-OR gate-based transformations successfully contributed toward generating smaller circuits compared to other state-of-the-art logic optimization tools
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