Parallel Processor Architecture with a New Algorithm for Simultaneous Processing of MIPS-Based Series Instructions

Processors are main part of the calculation and decision making of a system. Today, due to the increasing need of industry and technology to faster and more accurate computing power, design and manufacture of parallel processing units, has been very much considered. One of the most important processor families used in various devises is the MIPS processors. This processor family had been considered in the telecom and control industry as a reasonable choice. In this paper, new architecture based on this processor, with new parallel processing design, is provided to allow parallel execution of instructions dynamically. Ultimately, the processor efficiency to several fold will be increased. In this architecture, new ideas for the issuance of instructions in parallel, intelligent detection of conditional jumps and memory management are presented

Injecting multiple upsets in a SEU tolerant 8051 micro-controller

This paper investigates the behavior of a SEU tolerant 8051-like micro-controller protected by single error correction Hamming code in the presence of multiple upsets. Upsets were randomly injected in all sensitive parts of the design. The experiment was emulated in a Virtex FPGA platform. Results evaluate the robustness of the tolerant 8051 in a multiple upsets environmen