On-Chip Digital Decoupling Capacitance Methodology

Signal integrity has become a major problem in digital IC design. One cause of this problem is device scaling which results in a sharp reduction of supply voltage, creating stringent noise margin requirements to ensure functionality. Reductions in feature size also result in increased clock speeds leading to many different high frequency noise producing components. As on-chip area increases to allow for more computational capability, so does the amount of digital logic to be placed, magnifying the effects of noisy interconnect structures. Supply noise, modeled as AV = Ldi/dt , is caused by rapid current spikes during a rise or fall time. Decoupling capacitors often fill empty on-chip space for the purpose of limiting this noise. This work introduces a novel methodology that attempts to quantify and locate decoupling capacitors within a power distribution network. The bondwire attached on the periphery of the face of the die is taken to be the dominant source of inductance. It is shown that distributing capacitance closer to the switching elements is most effective at reducing supply noise. A chip has been designed using TSMC 90 nm technology that implements the ideas presented in this work. Simulation results show that noise fluctuations are high enough such that random placement of decoupling capacitance is not effective for large digital structures. The amount of interconnect generated on-chip noise increases with area, resulting in the need for an optimal decoupling scheme. As scaling continues, supply voltages and noise margins will decrease, creating the need for a robust decoupling capacitance methodology

Inductance Effects in RLC Trees

A closed form solution for characterizing voltage-based signals in an RLC tree is presented. The closed form solution is used to derive figures of merit to characterize the effects of inductance at a specific node in an RLC tree. The effective damping factor of the signal at a specific node in an RLC tree is shown to be one useful figure of merit. It is shown that as the effective damping factor of a signal increases, an RC model is sufficiently accurate to characterize the waveform. The rise time of the input signal driving an RLC tree is shown to be a second factor that affects the relative significance of inductance. As the rise time of the input signal increases as compared to the effective LC time constant at a specific node within an RLC tree, the signal at this node will no longer exhibit the effects of inductance. It is demonstrated that a single line analysis to determine the importance of including inductance to characterize an interconnect line that is a part of a tree is i..

c ○ World Scientific Publishing Company INDUCTANCE EFFECTS IN RLC TREES

A closed form solution for characterizing voltage-based signals in an RLC tree is presented. The closed form solution is used to derive figures of merit to characterize the effects of inductance at a specific node in an RLC tree. The effective damping factor of the signal at a specific node in an RLC tree is shown to be one useful figure of merit. It is shown that as the effective damping factor of a signal increases, an RC model is sufficiently accurate to characterize the waveform. The rise time of the input signal driving an RLC tree is shown to be a second factor that affects the relative significance of inductance. As the rise time of the input signal increases as compared to the effective LC time constant at a specific node within an RLC tree, the signal at this node will no longer exhibit the effects of inductance. It is demonstrated that a single line analysis to determine the importance of including inductance to characterize an interconnect line that is a part of a tree is invalid in many cases and can lead to erroneous conclusions. The error exhibited by single line analysis is due to the large interaction among the branches of the tree