Incorporating compiler feedback into the design of ASIPs

This paper presents a framework for providing feedback from an optimizing compiler into the design of an ASIP. The optimizing compiler is used to assess the hardware needs of a suite of applications to which the ASIP is to be tuned. By incorporating the compiler into the design process, the design space is increased as more information is provided at an earlier stage during the design process. Our initial study involves detecting potentially chainable operation sequences using scheduling techniques developed for exploiting instruction-level parallelism. Results of this study are included.