Improving Cache Performance through Tiling and Data Alignment

. We address the problem of improving the data cache performance of numerical applications -- specifically, those with blocked (or tiled) loops. We present DAT, a data alignment technique utilizing arraypadding, to improve program performance through minimizing cache conflict misses. We describe algorithms for selecting tile sizes for maximizing data cache utilization, and computing pad sizes for eliminating self-interference conflicts in the chosen tile. We also present a generalization of the technique to handle applications with several tiled arrays. Our experimental results comparing our technique with previous published approaches on machines with different cache configurations show consistently good performance on several benchmark programs, for a variety of problem sizes. 1 Introduction The growing disparity between processor and memory speeds makes the efficient utilization of cache memory a critical factor in determining program performance. While locality in instruction refe..