High-Voltage and Low-Leakage AlGaN/GaN Tri-Anode Schottky Diodes With Integrated Tri-Gate Transistors

We present AlGaN/GaN nanostructured Schottky barrier diodes (SBDs) on silicon substrate with high breakdown voltage (V-BR) and low reverse leakage current (I-R), based on a hybrid of tri-anode and tri-gate architectures. The fabricated SBDs presented a small turn-ON voltage (V-ON) of 0.76 +/- 0.05 V, since the tri-anode architecture formed direct Schottky contact to the 2-D electron gas (2DEG). The reverse characteristic was controlled electrostatically by an embedded tri-gate transistor, instead of relying only on the Schottky barrier. This resulted in low I-R below 10 and 100 nA/mm at large reverse biases up to 500 and 700 V, respectively. In addition, these devices exhibited record V-BR up to 1325 V at I-R of 1 mu A/mm, rendering an excellent high-power figure-of-merit (FOM) of 939 MW/cm(2) and demonstrating the significant potential of nanostructured GaN SBDs for future efficient power conversion

High Performance Tri-gate GaN Power MOSHEMTs on Silicon Substrate

We demonstrate high-performance GaN power metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) on silicon substrate based on a nanowire tri-gate architecture. The common issue of partial removal of carriers by nanowire etching in GaN tri-gate transistors was resolved mainly by optimized tri-gate geometry, including filling factor and trench width. The tri-gate reduced the OFF-state leakage current (I-OFF) and the subthreshold slope, increased the ON/OFF ratio, and improved the breakdown voltage (V-BR) of the device. With a gate-to-drain separation (L-GD) of 5 mu m, the tri-gate MOSHEMTs exhibited V-BR of 792 V at I-OFF of 0.3 mu A/mm, along with a small specific ON-resistance (R-ON, (SP)) of 0.91 +/- 0.08 m Omega.cm(2). With L-GD of 15 mu m, hard V-BR of 1755 V at I-OFF of 45 mu A/mm with high soft V-BR of 1370 V at I-OFF = 1 mu A/mm were achieved, rendering excellent high power figure of merits (FOMs) up to 1.25 GW/cm(2). These results unveil the significant potential of nanostructured GaN transistors for future power applications

3D GaN nanoarchitecture for field-effect transistors

The three-dimensionality of 3D GaN field-effect transistors (FETs) provides them with unique advantages compared to their planar counterparts, introducing a promising path towards future FETs beyond Moore's law. Similar to today's Si processor technology, 3D GaN FETs offer multi-gate structures that provide excellent electrostatic control over the channel and enable very low subthreshold swing values close to the theoretical limit. Various concepts have been demonstrated, including both lateral and vertical devices with GaN nanowire (NW) or nanofin (NF) geometries. Outstanding transport properties were achieved with laterally contacted NWs that were grown in a bottom-up approach and transferred onto an insulating substrate. For higher power application, vertical FETs based on regular arrays of GaN nanostructures are particularly promising due to their parallel integration capability and large sidewall surfaces, which can be utilized as channel area. In this paper, we review the current status of 3D GaN FETs and discuss their concepts, fabrication techniques, and performances. In addition to the potential benefits, reliability issues and difficulties that may arise in complex 3D processing are discussed, which need to be tackled to pave the way for future switching applications