Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality

Cell-aware test (CAT) explicitly targets faults caused by defects inside library cells to improve test quality, compared with conventional automatic test pattern generation (ATPG) approaches, which target faults only at the boundaries of library cells. The CAT methodology consists of two stages. Stage 1, based on dedicated analog simulation, library characterization per cell identifies which cell-level test pattern detects which cell-internal defect; this detection information is encoded in a defect detection matrix (DDM). In Stage 2, with the DDMs as inputs, cell-aware ATPG generates chip-level test patterns per circuit design that is build up of interconnected instances of library cells. This paper focuses on Stage 1, library characterization, as both test quality and cost are determined by the set of cell-internal defects identified and simulated in the CAT tool flow. With the aim to achieve the best test quality, we first propose an approach to identify a comprehensive set, referred to as full set, of potential open- and short-defect locations based on cell layout. However, the full set of defects can be large even for a single cell, making the time cost of the defect simulation in Stage 1 unaffordable. Subsequently, to reduce the simulation time, we collapse the full set to a compact set of defects which serves as input of the defect simulation. The full set is stored for the diagnosis and failure analysis. With inspecting the simulation results, we propose a method to verify the test quality based on the compact set of defects and, if necessary, to compensate the test quality to the same level as that based on the full set of defects. For 351 combinational library cells in Cadence’s GPDK045 45nm library, we simulate only 5.4% defects from the full set to achieve the same test quality based on the full set of defects. In total, the simulation time, via linear extrapolation per cell, would be reduced by 96.4% compared with the time based on the full set of defects

Design and application of reconfigurable circuits and systems

Open Acces

Investigation into voltage and process variation-aware manufacturing test

Increasing integration and complexity in IC design provides challenges for manufacturing testing. This thesis studies how process and supply voltage variation influence defect behaviour to determine the impact on manufacturing test cost and quality. The focus is on logic testing of static CMOS designs with respect to two important defect types in deep submicron CMOS: resistive bridges and full opens. The first part of the thesis addresses testing for resistive bridge defects in designs with multiple supply voltage settings. To enable analysis, a fault simulator is developed using a supply voltage-aware model for bridge defect behaviour. The analysis shows that for high defect coverage it is necessary to perform test for more than one supply voltage setting, due to supply voltage-dependent behaviour. A low-cost and effective test method is presented consisting of multi-voltage test generation that achieves high defect coverage and test set size reduction without compromise to defect coverage. Experiments on synthesised benchmarks with realistic bridge locations validate the proposed method.The second part focuses on the behaviour of full open defects under supply voltage variation. The aim is to determine the appropriate value of supply voltage to use when testing. Two models are considered for the behaviour of full open defects with and without gate tunnelling leakage influence. Analysis of the supply voltage-dependent behaviour of full open defects is performed to determine if it is required to test using more than one supply voltage to detect all full open defects. Experiments on synthesised benchmarks using an extended version of the fault simulator tool mentioned above, measure the quantitative impact of supply voltage variation on defect coverage.The final part studies the impact of process variation on the behaviour of bridge defects. Detailed analysis using synthesised ISCAS benchmarks and realistic bridge model shows that process variation leads to additional faults. If process variation is not considered in test generation, the test will fail to detect some of these faults, which leads to test escapes. A novel metric to quantify the impact of process variation on test quality is employed in the development of a new test generation tool, which achieves high bridge defect coverage. The method achieves a user-specified test quality with test sets which are smaller than test sets generated without consideration of process variation

Fault simulation for structural testing of analogue integrated circuits

In this thesis the ANTICS analogue fault simulation software is described which provides a statistical approach to fault simulation for accurate analogue IC test evaluation. The traditional figure of fault coverage is replaced by the average probability of fault detection. This is later refined by considering the probability of fault occurrence to generate a more realistic, weighted test metric. Two techniques to reduce the fault simulation time are described, both of which show large reductions in simulation time with little loss of accuracy. The final section of the thesis presents an accurate comparison of three test techniques and an evaluation of dynamic supply current monitoring. An increase in fault detection for dynamic supply current monitoring is obtained by removing the DC component of the supply current prior to measurement

Diagnosis of systematic defects based on design-for-manufacturability guidelines

All products in the Very-Large-Scale-Integrated-Circuit (VLSIC) industry go through three major stages of production - Design, Verification and Manufacturing. Unfortunately, neither of these stages are truly perfect, hence we need two more sub-stages of manufacturing, namely Testing and Defect Diagnosis to prevent imperfections in ICs. Testing is used to generate test vectors to validate the functionality of the Device-under-Test (DUT), and Defect Diagnosis is the process of identifying the root-cause of a failing chip, i.e., the location and nature of defect. Systematic defects are unintended structural and material changes at specific locations with a higher probability of failure due to repeating manufacturing imperfections. While Design-For-Manufacturability (DFM) guidelines are not always applied due to limited resources like circuit area and design time, enforcing these guidelines helps in ensuring sufficient product yields by preventing systematic defects. However, even if the DFM guidelines are strictly enforced, systematic defects may still occur as complete information about the process and manufacturing is not available due to reducing available time-to-market for chips. ^ An earlier work used DFM guidelines as a basis for modeling of defects, and diagnostic test generation. Under this framework, a circuit is processed to identify layout locations that violate DFM rules. Next, these coordinates are mapped and translated to faults based on different fault models including stuck-at-faults, bridging faults and transition faults. ^ The goal of this thesis is to perform systematic defect diagnosis and analyze the accuracy of diagnosis under the same DFM framework. Thus, systematic defect candidates are generated from DFM guidelines and the generated faultlist is used to perform diagnosis. Because defects may not always be systematic, a new heuristic to dynamically switch between DFM and non-DFM faultlists has also been implemented. This presents us with the best option to follow to further optimize the accuracy of diagnosis. The results demonstrate that the DFM framework can be used to improve the accuracy of diagnosis with minimal resource requirements

Defect-based testing of LTS digital circuits

A Defect-Based Test (DBT) methodology for Superconductor Electronics (SCE) is presented in this thesis, so that commercial production and efficient testing of systems can be implemented in this technology in the future. In the first chapter, the features and prospects for SCE have been presented. The motivation for this research and the outline of the thesis were also described in Chapter 1. It has been shown that high-end applications such as Software-Defined Radio (SDR) and petaflop computers which are extremely difficult to implement in top-of-the-art semiconductor technologies can be realised using SCE. But, a systematic structural test methodology had yet to be developed for SCE and has been addressed in this thesis. A detailed introduction to Rapid Single-Flux Quantum (RSFQ) circuits was presented in Chapter 2. A Josephson Junction (JJ) was described with associated theory behind its operation. The JJ model used in the simulator used in this research work was also presented. RSFQ logic with logic protocols as well as the design and implementation of an example D-type flip-flop (DFF) was also introduced. Finally, advantages and disadvantages of RSFQ circuits have been discussed with focus on the latest developments in the field. Various techniques for testing RSFQ circuits were discussed in Chapter 3. A Process Defect Monitor (PDM) approach was presented for fabrication process analysis. The presented defect-monitor structures were used to gather measurement data, to find the probability of the occurrence of defects in the process which forms the first step for Inductive Fault Analysis (IFA). Results from measurements on these structures were used to create a database for defects. This information can be used as input for performing IFA. "Defect-sprinkling" over a fault-free circuit can be carried out according to the measured defect densities over various layers. After layout extraction and extensive fault simulation, the resulting information will indicate realistic faults. In addition, possible Design-for-Testability (DfT) schemes for monitoring Single-Flux Quantum (SFQ) pulses within an RSFQ circuit has also been discussed in Chapter 3. The requirement for a DfT scheme is inevitable for RSFQ circuits because of their very high frequency of operation and very low operating temperature. It was demonstrated how SFQ pulses can be monitored at an internal node of an SCE circuit, introducing observability using Test-Point Insertion (TPI). Various techniques were discussed for the introduction of DfT and to avoid the delay introduced by the DfT structure if it is required. The available features in the proposed design for customising the detector make it attractive for a detailed DBT of RSFQ circuits. The control of internal nodes has also been illustrated using TPI. The test structures that were designed and implemented to determine the occurrence of defects in the processes can also be used to locate the position for the insertion of the above mentioned DfT structures

Fault modeling, delay evaluation and path selection for delay test under process variation in nano-scale VLSI circuits

Delay test in nano-scale VLSI circuits becomes more difficult with shrinking technology feature sizes and rising clock frequencies. In this dissertation, we study three challenging issues in delay test: fault modeling, variational delay evaluation and path selection under process variation. Previous research of fault modeling on resistive spot defects, such as resistive opens and bridges in the interconnect, and resistive shorts in devices, lacked an accurate fault model. As a result it was difficult to perform fault simulation and select the best vectors. Conventional methods to compute variational delay under process variation are either slow or inaccurate. On the problem of path selection under process variation, previous approaches either choose too many paths, or missed the path that is necessary to be tested. We present new solutions in this dissertation. A new fault model that clearly and comprehensively expresses the relationship between electrical behaviors and resistive spots is proposed. Then the effect of process variations on path delays is modeled with a linear function and a fast method to compute coefficients of the linear function is also derived. Finally, we present the new path pruning algorithms that efficiently prune unimportant paths for test, and as a result we select as few as possible paths for test while the fault coverage is satisfied. The experimental results show that the new solutions are efficient and accurate

Interconnect yield analysis and fault tolerance for field programmable gate arrays

Imperial Users onl