932 research outputs found
Improved Decoding of Staircase Codes: The Soft-aided Bit-marking (SABM) Algorithm
Staircase codes (SCCs) are typically decoded using iterative bounded-distance
decoding (BDD) and hard decisions. In this paper, a novel decoding algorithm is
proposed, which partially uses soft information from the channel. The proposed
algorithm is based on marking certain number of highly reliable and highly
unreliable bits. These marked bits are used to improve the
miscorrection-detection capability of the SCC decoder and the error-correcting
capability of BDD. For SCCs with -error-correcting
Bose-Chaudhuri-Hocquenghem component codes, our algorithm improves upon
standard SCC decoding by up to ~dB at a bit-error rate (BER) of
. The proposed algorithm is shown to achieve almost half of the gain
achievable by an idealized decoder with this structure. A complexity analysis
based on the number of additional calls to the component BDD decoder shows that
the relative complexity increase is only around at a BER of .
This additional complexity is shown to decrease as the channel quality
improves. Our algorithm is also extended (with minor modifications) to product
codes. The simulation results show that in this case, the algorithm offers
gains of up to ~dB at a BER of .Comment: 10 pages, 12 figure
Binary Message Passing Decoding of Product-like Codes
We propose a novel binary message passing decoding algorithm for product-like
codes based on bounded distance decoding (BDD) of the component codes. The
algorithm, dubbed iterative BDD with scaled reliability (iBDD-SR), exploits the
channel reliabilities and is therefore soft in nature. However, the messages
exchanged by the component decoders are binary (hard) messages, which
significantly reduces the decoder data flow. The exchanged binary messages are
obtained by combining the channel reliability with the BDD decoder output
reliabilities, properly conveyed by a scaling factor applied to the BDD
decisions. We perform a density evolution analysis for generalized low-density
parity-check (GLDPC) code ensembles and spatially coupled GLDPC code ensembles,
from which the scaling factors of the iBDD-SR for product and staircase codes,
respectively, can be obtained. For the white additive Gaussian noise channel,
we show performance gains up to dB and dB for product and
staircase codes compared to conventional iterative BDD (iBDD) with the same
decoder data flow. Furthermore, we show that iBDD-SR approaches the performance
of ideal iBDD that prevents miscorrections.Comment: Accepted for publication in the IEEE Transactions on Communication
Binary Message Passing Decoding of Product Codes Based on Generalized Minimum Distance Decoding
We propose a binary message passing decoding algorithm for product codes
based on generalized minimum distance decoding (GMDD) of the component codes,
where the last stage of the GMDD makes a decision based on the Hamming distance
metric. The proposed algorithm closes half of the gap between conventional
iterative bounded distance decoding (iBDD) and turbo product decoding based on
the Chase--Pyndiah algorithm, at the expense of some increase in complexity.
Furthermore, the proposed algorithm entails only a limited increase in data
flow compared to iBDD.Comment: Invited paper to the 53rd Annual Conference on Information Sciences
and Systems (CISS), Baltimore, MD, March 2019. arXiv admin note: text overlap
with arXiv:1806.1090
RS + LDPC-Staircase Codes for the Erasure Channel: Standards, Usage and Performance
Application-Level Forward Erasure Correction (AL-FEC) codes are a key element of telecommunication systems. They are used to recover from packet losses when retransmission are not feasible and to optimize the large scale distribution of contents. In this paper we introduce Reed-Solomon/LDPCStaircase codes, two complementary AL-FEC codes that have recently been recognized as superior to Raptor codes in the context of the 3GPP-eMBMS call for technology [1]. After a brief introduction to the codes, we explain how to design high performance codecs which is a key aspect when targeting embedded systems with limited CPU/battery capacity. Finally we present the performances of these codes in terms of erasure correction capabilities and encoding/decoding speed, taking advantage of the 3GPP-eMBMS results where they have been ranked first
Low-Complexity LP Decoding of Nonbinary Linear Codes
Linear Programming (LP) decoding of Low-Density Parity-Check (LDPC) codes has
attracted much attention in the research community in the past few years. LP
decoding has been derived for binary and nonbinary linear codes. However, the
most important problem with LP decoding for both binary and nonbinary linear
codes is that the complexity of standard LP solvers such as the simplex
algorithm remains prohibitively large for codes of moderate to large block
length. To address this problem, two low-complexity LP (LCLP) decoding
algorithms for binary linear codes have been proposed by Vontobel and Koetter,
henceforth called the basic LCLP decoding algorithm and the subgradient LCLP
decoding algorithm.
In this paper, we generalize these LCLP decoding algorithms to nonbinary
linear codes. The computational complexity per iteration of the proposed
nonbinary LCLP decoding algorithms scales linearly with the block length of the
code. A modified BCJR algorithm for efficient check-node calculations in the
nonbinary basic LCLP decoding algorithm is also proposed, which has complexity
linear in the check node degree.
Several simulation results are presented for nonbinary LDPC codes defined
over Z_4, GF(4), and GF(8) using quaternary phase-shift keying and
8-phase-shift keying, respectively, over the AWGN channel. It is shown that for
some group-structured LDPC codes, the error-correcting performance of the
nonbinary LCLP decoding algorithms is similar to or better than that of the
min-sum decoding algorithm.Comment: To appear in IEEE Transactions on Communications, 201
Density Evolution for Deterministic Generalized Product Codes with Higher-Order Modulation
Generalized product codes (GPCs) are extensions of product codes (PCs) where
coded bits are protected by two component codes but not necessarily arranged in
a rectangular array. It has recently been shown that there exists a large class
of deterministic GPCs (including, e.g., irregular PCs, half-product codes,
staircase codes, and certain braided codes) for which the asymptotic
performance under iterative bounded-distance decoding over the binary erasure
channel (BEC) can be rigorously characterized in terms of a density evolution
analysis. In this paper, the analysis is extended to the case where
transmission takes place over parallel BECs with different erasure
probabilities. We use this model to predict the code performance in a coded
modulation setup with higher-order signal constellations. We also discuss the
design of the bit mapper that determines the allocation of the coded bits to
the modulation bits of the signal constellation.Comment: invited and accepted paper for the special session "Recent Advances
in Coding for Higher Order Modulation" at the International Symposium on
Turbo Codes & Iterative Information Processing, Brest, France, 201
Staircase Codes: FEC for 100 Gb/s OTN
Staircase codes, a new class of forward-error-correction (FEC) codes suitable
for high-speed optical communications, are introduced. An ITU-T
G.709-compatible staircase code with rate R=239/255 is proposed, and FPGA-based
simulation results are presented, exhibiting a net coding gain (NCG) of 9.41 dB
at an output error rate of 1E-15, an improvement of 0.42 dB relative to the
best code from the ITU-T G.975.1 recommendation. An error floor analysis
technique is presented, and the proposed code is shown to have an error floor
at 4.0E-21.Comment: To appear in IEEE/OSA J. of Lightwave Technolog
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