Hardware Trojan Detection and Mitigation in NoC using Key authentication and Obfuscation Techniques

Today's Multiprocessor System-on-Chip (MPSoC) contains many cores and integrated circuits. Due to the current requirements of communication, we make use of Network-on-Chip (NoC) to obtain high throughput and low latency. NoC is a communication architecture used in the processor cores to transfer  data from source to destination through several nodes. Since NoC deals with on-chip interconnection for data transmission, it will be a good prey for data leakage and other security attacks. One such way of attacking is done by a third-party vendor introducing Hardware Trojans (HTs) into routers of NoC architecture. This can cause packets to traverse in wrong paths, leak/extract information and cause Denial-of-Service (DoS) degrading the system performance. In this paper, a novel HT detection and mitigation approach using obfuscation and key-based authentication technique is proposed. The proposed technique prevents any illegal transitions between routers thereby protecting data from malicious activities, such as packet misrouting and information leakage. The proposed technique is evaluated on a 4x4 NoC architecture under synthetic traffic pattern and benchmarks, the hardware model is synthesized in Cadence Tool with 90nm technology. The introduced Hardware Trojan affects 8% of packets passing through infected router. Experimental results demonstrate that the proposed technique prevents those 10-15% of packets infected from the HT effect. Our proposed work has negligible power and area overhead of 8.6% and  2% respectively

Improved flow control for minimal fully adaptive routing in 2D mesh NoC

Routing algorithm has a significant impact on the overall performance of network-on-chip (NoC) based system due to the unbalanced nature of NoC traffic. In this paper, we propose an improved flow control for implementing fully adaptive routing algorithm on 2D mesh based NoC. Our proposed NoC router allows packet exchanges from escape virtual channels (EVCs) to adaptive VCs (AVCs). It also relaxes the atomic VC reallocation constraint for all EVCs as well as AVCs, which are located in router's local, east and west ports of the router. This approach guarantees that the abovementioned conditions still result in a deadlock-free routing. The proposed fully adaptive NoC outperforms the conventional fully adaptive router and partially adaptive router that uses odd-even routing by 80% and 25% higher average saturation injection ratio, respectively