Implications of VHDL Timing Models on Simulation and Software Synthesis

In this paper, we address the timing semantics of the delay models handled by VHDL. A formal model is used to characterize the runtime work required to resolve multiple assignments to signals for each of these models. Subsets of these timing models which require minimal work at runtime for resolution of multiple assignments are identified. Algorithms for generation of efficient code for simulation and synthesis in these restricted timing models are given. We present runtimes of our implementation of a simulator which uses these algorithms. 1 Introduction VHDL provides a rich set of features to model hardware at different levels of abstraction. This is particularly true of the flexibility present in the delay models supported by the language and the timing semantics associated with them. Detailed timing behavior at low levels of abstraction can be modeled by lumping the delay characteristics of devices as delays associated with signal assignments. This is useful when simulating systems ..