Empirical timing analysis of CPUs and delay fault tolerant design using partial redundancy

The operating clock frequency is determined by the longest signal propagation delay, setup/hold time, and timing margin. These are becoming less predictable with the increasing design complexity and process miniaturization. The difficult challenge is then to ensure that a device operating at its clock frequency is error-free with quantifiable assurance. Effort at device-level engineering will not suffice for these circuits exhibiting wide process variation and heightened sensitivities to operating condition stress. Logic-level redress of this issue is a necessity and we propose a design-level remedy for this timing-uncertainty problem. The aim of the design and analysis approaches presented in this dissertation is to provide framework, SABRE, wherein an increased operating clock frequency can be achieved. The approach is a combination of analytical modeling, experimental analy- sis, hardware /time-redundancy design, exception handling and recovery techniques. Our proposed design replicates only a necessary part of the original circuit to avoid high hardware overhead as in triple-modular-redundancy (TMR). The timing-critical combinational circuit is path-wise partitioned into two sections. The combinational circuits associated with long paths are laid out without any intrusion except for the fan-out connections from the first section of the circuit to a replicated second section of the combinational circuit. Thus only the second section of the circuit is replicated. The signals fanning out from the first section are latches, and thus are far shorter than the paths spanning the entire combinational circuit. The replicated circuit is timed at a subsequent clock cycle to ascertain relaxed timing paths. This insures that the likelihood of mistiming due to stress or process variation is eliminated. During the subsequent clock cycle, the outcome of the two logically identical, yet time-interleaved, circuit outputs are compared to detect faults. When a fault is detected, the retry sig- nal is triggered and the dynamic frequency-step-down takes place before a pipe flush, and retry is issued. The significant timing overhead associated with the retry is offset by the rarity of the timing violation events. Simulation results on ISCAS Benchmark circuits show that 10% of clock frequency gain is possible with 10 to 20 % of hardware overhead of replicated timing-critical circuit

Contribution à l'intégration de la fiabilité dansle flôt de conception des circuits intégrés fondée sur l'utilisation d'un langage de description comportementale VHDL-AMS

L'évolution croissante des technologies CMOS entraîne le renouvellement des techniques de prédiction de la fiabilité des circuits. Les méthodes statistiques ne suffisent plus pour évaluer la fiabilité des circuits à forte intégration. De nouvelles techniques de prédiction de fiabilité doivent être définies et mises en place afin de répondre rapidement aux contraintes d'analyse de la fiabilité. Une étude de la fiabilité des circuits CMOS doit être prise en charge en amont de la production. Pour cela, il est nécessaire de tenir compte de la dépendance des dispositifs élémentaires aux mécanismes de dégradation au cours du flot de conception des circuits. A partir d'un modèle électrique de dégradation du transistor MOSFET, fondé sur le langage de description comportementale VHDL-AMS, il est démontré qu'une prédiction de la fiabilité des circuits CMOS est réalisable à partir de simulations électriques. Une validation est réalisée à partir d'un circuit CMOS de démonstration : l'amplificateur opérationnel de transconductance. L'intérêt de cette méthode est sa reproductibilité pour la construction de modèles VHDL-AMS de dégradation de circuits CMOS d'abstraction supérieure dans le but d'analyser la fiabilité des systèmes.The increasing CMOS process evolution involves the renewal of the techniques to predict the circuits reliability. The statistical methods are not enough any more to evaluate the reliability of the VLSI circuits. New techniques of reliability prediction must be defined and implemented in order to quickly answer to the constraints of reliability analysis. A study of the CMOS circuits reliability must be dealt with upstream production. Then, it is necessary to hold account the dependence of the elementary devices with the degradation mechanisms during the circuit design flow. From a degradation electric model of transistor MOSFET, founded on the VHDL-AMS behavioral modelling language, it is shown that a prediction of the CMOS circuits reliability is realizable starting from electric simulations. A validation is carried out starting from a CMOS circuit demonstration : the operational transconductance amplifier. The method interest is its reproducibility to build degradation VHDL-AMS models of CMOS circuits with higher description abstraction in order to analyze the reliability of the electronics systems