Deriving Good LDPC Convolutional Codes from LDPC Block Codes

Low-density parity-check (LDPC) convolutional codes are capable of achieving excellent performance with low encoding and decoding complexity. In this paper we discuss several graph-cover-based methods for deriving families of time-invariant and time-varying LDPC convolutional codes from LDPC block codes and show how earlier proposed LDPC convolutional code constructions can be presented within this framework. Some of the constructed convolutional codes significantly outperform the underlying LDPC block codes. We investigate some possible reasons for this "convolutional gain," and we also discuss the --- mostly moderate --- decoder cost increase that is incurred by going from LDPC block to LDPC convolutional codes.Comment: Submitted to IEEE Transactions on Information Theory, April 2010; revised August 2010, revised November 2010 (essentially final version). (Besides many small changes, the first and second revised versions contain corrected entries in Tables I and II.

Efficient Termination of Spatially-Coupled Codes

Spatially-coupled low-density parity-check codes attract much attention due to their capacity-achieving performance and a memory-efficient sliding-window decoding algorithm. On the other hand, the encoder needs to solve large linear equations to terminate the encoding process. In this paper, we propose modified spatially-coupled codes. The modified (\dl,\dr,L) codes have less rate-loss, i.e., higher coding rate, and have the same threshold as (\dl,\dr,L) codes and are efficiently terminable by using an accumulator

A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes

This paper propose a decoder architecture for low-density parity-check convolutional code (LDPCCC). Specifically, the LDPCCC is derived from a quasi-cyclic (QC) LDPC block code. By making use of the quasi-cyclic structure, the proposed LDPCCC decoder adopts a dynamic message storage in the memory and uses a simple address controller. The decoder efficiently combines the memories in the pipelining processors into a large memory block so as to take advantage of the data-width of the embedded memory in a modern field-programmable gate array (FPGA). A rate-5/6 QC-LDPCCC has been implemented on an Altera Stratix FPGA. It achieves up to 2.0 Gb/s throughput with a clock frequency of 100 MHz. Moreover, the decoder displays an excellent error performance of lower than $10^{-13}$ at a bit-energy-to-noise-power-spectral-density ratio ($E_b/N_0$) of 3.55 dB.Comment: accepted to IEEE Transactions on Circuits and Systems

Short Block-length Codes for Ultra-Reliable Low-Latency Communications

This paper reviews the state of the art channel coding techniques for ultra-reliable low latency communication (URLLC). The stringent requirements of URLLC services, such as ultra-high reliability and low latency, have made it the most challenging feature of the fifth generation (5G) mobile systems. The problem is even more challenging for the services beyond the 5G promise, such as tele-surgery and factory automation, which require latencies less than 1ms and failure rate as low as $10^{-9}$. The very low latency requirements of URLLC do not allow traditional approaches such as re-transmission to be used to increase the reliability. On the other hand, to guarantee the delay requirements, the block length needs to be small, so conventional channel codes, originally designed and optimised for moderate-to-long block-lengths, show notable deficiencies for short blocks. This paper provides an overview on channel coding techniques for short block lengths and compares them in terms of performance and complexity. Several important research directions are identified and discussed in more detail with several possible solutions.Comment: Accepted for publication in IEEE Communications Magazin

Spatially Coupled LDPC Codes Constructed from Protographs

In this paper, we construct protograph-based spatially coupled low-density parity-check (SC-LDPC) codes by coupling together a series of L disjoint, or uncoupled, LDPC code Tanner graphs into a single coupled chain. By varying L, we obtain a flexible family of code ensembles with varying rates and frame lengths that can share the same encoding and decoding architecture for arbitrary L. We demonstrate that the resulting codes combine the best features of optimized irregular and regular codes in one design: capacity approaching iterative belief propagation (BP) decoding thresholds and linear growth of minimum distance with block length. In particular, we show that, for sufficiently large L, the BP thresholds on both the binary erasure channel (BEC) and the binary-input additive white Gaussian noise channel (AWGNC) saturate to a particular value significantly better than the BP decoding threshold and numerically indistinguishable from the optimal maximum a-posteriori (MAP) decoding threshold of the uncoupled LDPC code. When all variable nodes in the coupled chain have degree greater than two, asymptotically the error probability converges at least doubly exponentially with decoding iterations and we obtain sequences of asymptotically good LDPC codes with fast convergence rates and BP thresholds close to the Shannon limit. Further, the gap to capacity decreases as the density of the graph increases, opening up a new way to construct capacity achieving codes on memoryless binary-input symmetric-output (MBS) channels with low-complexity BP decoding.Comment: Submitted to the IEEE Transactions on Information Theor