1 research outputs found
Implementation and Analysis of Stable PUFs Using Gate Oxide Breakdown
We implement and analyze highly stable PUFs using two random gate oxide
breakdown mechanisms: plasma induced breakdown and voltage stressed breakdown.
These gate oxide breakdown PUFs can be easily implemented in commercial silicon
processes, and they are highly stable. We fabricated bit generation units for
the stable PUFs on 99 testchips with 65nm CMOS bulk technology. Measurement
results show that the plasma induced breakdown can generate complete stable
responses. For the voltage stressed breakdown, the responses are with 0.12\%
error probability at a worst case corner, which can be effectively accommodated
by taking the majority vote from multiple measurements. Both PUFs show
significant area reduction compared to SRAM PUF. We compare methods for
evaluating the security level of PUFs such as min-entropy, mutual information
and guesswork as well as inter- and intra-FHD, and the popular NIST test suite.
We show that guesswork can be viewed as a generalization of min-entropy and
mutual information. In addition, we analyze our testchip data and show through
various statistical distance measures that the bits are independent. Finally,
we propose guesswork as a new statistical measure for the level of statistical
independence that also has an operational meaning in terms of security