287 research outputs found
Neuro-memristive Circuits for Edge Computing: A review
The volume, veracity, variability, and velocity of data produced from the
ever-increasing network of sensors connected to Internet pose challenges for
power management, scalability, and sustainability of cloud computing
infrastructure. Increasing the data processing capability of edge computing
devices at lower power requirements can reduce several overheads for cloud
computing solutions. This paper provides the review of neuromorphic
CMOS-memristive architectures that can be integrated into edge computing
devices. We discuss why the neuromorphic architectures are useful for edge
devices and show the advantages, drawbacks and open problems in the field of
neuro-memristive circuits for edge computing
Examining the Role and Limits of Batchnorm Optimization to Mitigate Diverse Hardware-noise in In-memory Computing
In-Memory Computing (IMC) platforms such as analog crossbars are gaining
focus as they facilitate the acceleration of low-precision Deep Neural Networks
(DNNs) with high area- & compute-efficiencies. However, the intrinsic
non-idealities in crossbars, which are often non-deterministic and non-linear,
degrade the performance of the deployed DNNs. In addition to quantization
errors, most frequently encountered non-idealities during inference include
crossbar circuit-level parasitic resistances and device-level non-idealities
such as stochastic read noise and temporal drift. In this work, our goal is to
closely examine the distortions caused by these non-idealities on the
dot-product operations in analog crossbars and explore the feasibility of a
nearly training-less solution via crossbar-aware fine-tuning of batchnorm
parameters in real-time to mitigate the impact of the non-idealities. This
enables reduction in hardware costs in terms of memory and training energy for
IMC noise-aware retraining of the DNN weights on crossbars.Comment: Accepted in Great Lakes Symposium on VLSI 2023 (GLSVLSI 2023)
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